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Low-Noise Amplifier. RF Receiver. Antenna. BPF1. LNA. BPF2. Mixer. BPF3. IF Amp. Demodulator. RF front end. LO. Low-Noise Amplifier. First gain stage in receiver Amplify weak signal Significant impact on noise performance Dominate input-referred noise of front end

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rf receiver
RF Receiver

Antenna

BPF1

LNA

BPF2

Mixer

BPF3

IF Amp

Demodulator

RF front end

LO

low noise amplifier3
Low-Noise Amplifier
  • First gain stage in receiver
    • Amplify weak signal
  • Significant impact on noise performance
    • Dominate input-referred noise of front end
  • Impedance matching
    • Efficient power transfer
    • Better noise performance
    • Stable circuit
lna design consideration
LNA Design Consideration
  • Noise performance
  • Power transfer
  • Impedance matching
  • Power consumption
  • Bandwidth
  • Stability
  • Linearity
noise figure
Noise Figure
  • Definition
  • As a function of device

G: Power gain of the device

nf of cascaded stages
NF of Cascaded Stages

Sin/Nin

Sout/Nout

G1, N1, NF1

Gi, Ni, NFi

GK, NK, NFK

  • Overall NF dominated by NF1

[1] F. Friis, “Noise Figure of Radio Receivers,” Proc. IRE, Vol. 32, pp.419-422, July 1944.

simple model of noise in mosfet
Simple Model of Noise in MOSFET
  • Flicker noise
    • Dominant at low frequency
  • Thermal noise
    • g: empirical constant

2/3 for long channel

much larger for short channel

    • PMOS has less thermal noise
  • Input-inferred noise

Vg

Id

Vi

noise approximation
Noise Approximation

Noise spectral density

1/f noise

Thermal noise dominant

Thermal noise

Frequency

Band of interest

power transfer and impedance matching
Power Transfer and Impedance Matching
  • Power delivered to load
  • Maxim available power

Rs

jXs

jXL

Vs

I

V

RL

  • Impedance matching
    • Load and source impedances conjugate pair
    • Real part matched to 50 ohm
available power
Available Power

Equal power on load and source resistors

reflection coefficient12
Reflection Coefficient

No reflectionMaximum power transfer

s parameters
S-Parameters
  • Parameters for two-port system analysis
  • Suitable for distributive elements
  • Inputs and outputs expressed in powers
    • Transmission coefficients
    • Reflection coefficients
s parameters14
S-Parameters

a1

b2

S21

S11

S22

S12

b1

a2

s parameters15
S-Parameters
  • S11 – input reflection coefficient with the output matched
  • S21 – forward transmission gain or loss
  • S12 – reverse transmission or isolation
  • S22 – output reflection coefficient with the input matched
s parameters16
S-Parameters

I1

I2

S

Z1

Z2

Vs1

V1

V2

Vs2

stability condition
Stability Condition
  • Necessary condition

where

  • Stable iff

where

a first lna example
A First LNA Example
  • Assume
    • No flicker noise
    • ro = infinity
    • Cgd = 0
    • Reasonable for appropriate bandwidth
  • Effective transconductance

io

Rs

Vs

Rs

4kTRs

Vs

Vgs

gmVgs

4kTggm

power gain
Power Gain
  • Voltage input
  • Current output
noise figure calculation
Noise Figure Calculation
  • Power ratio @ output
    • Device noise + input-induced noise
    • Input-induced noise
unity current gain frequency

Device

iout

iin

Unity Current Gain Frequency

Ai

fT

0dB

f

frequency

small signal model of mosfet
Small-Signal Model of MOSFET
  • Cgs
  • Cgd
  • rds
  • Cdb
  • Rg: Gate resistance
  • ri: Channel charging resistance

i2

i1

V1

V2

i1

i2

Rg

Cgd

Cdb

Cgs

V’gs

V2

rds

V1

ri

gmV’gs

w t calculation

i1

i2

Rg

Cgd

Cgs

V’gs

gmV’gs

V1

ri

wT Calculation

i1

i2

Rg

Cgd

Cdb

Cgs

V’gs

gmV’gs

rds

V1

ri

w t of nmos and pmos
wT of NMOS and PMOS
  • 0.25um CMOS Process*

Set:

Solve for wT

[2] Tajinder Manku, “Microwave CMOS - Device Physics and Design,” IEEE J. Solid-State Circuits, vol. 34, pp. 277 - 285, March 1999.

noise performance
Noise Performance
  • Low frequency
    • Rsgm >> g ~ 1
    • gm >> 1/50 @ Rs = 50 ohm
    • Power consuming
  • CMOS technology
    • gm/ID lower than other tech
    • wT lower than other tech
review of first example
Review of First Example
  • No impedance matching
    • Capacitive input impedance
    • Output not matched
  • Power transfer
    • S11=(1-sRCgs)/(1+sRCgs)
    • S21=2Rgm/(1+sRCgs), R=Rs=RL
  • Power consumption
    • High power for NF
    • High power for S21
impedance matching for lna
Impedance Matching for LNA
  • Resistive termination
  • Series-shunt feedback
  • Common-gate connection
  • Inductor degeneration
resistive termination
Resistive Termination

io

Rs

4kTggm

4kT/Rs

4kT/RI

Vs

RI

Is

Rs

RI

Vgs

gmVgs

  • Current-current power gain
  • Noise figure
comparison with previous example
Comparison with Previous Example
  • Previous example
  • Resistive-termination

Introduced by input resistance

Signal attenuated

summary resistive termination
Summary - Resistive Termination
  • Noise performance
    • Low-frequency approximation
    • Input matched Rs = RI = R
  • Broadband input match
  • Attenuate signal
  • Introduce noise due to RI
  • NF > 3 dB (best case)
series shunt feedback
Series-Shunt Feedback

RF

  • Broadband matching
  • Could be noisy

RL

Rs

Vs

Ra

iout

Rs

RF

RL

Cgs

Vgs

gmVgs

Vs

Ra

common gate structure
Common-Gate Structure

4kTggm

RL

Rs

RL

Rs

4kTRs

gmVgs

Vs

Vgs

RL

Rs

4kTRs

gm

Vs

Vgs

gmVgs

4kTggm

input impedance of cg structure
Input Impedance of CG Structure
  • Input impedance

Yin=gm+sCgs

  • Input-impedance matching
    • Low frequency approximation
    • Direct without passive components

1/gm=Rs=50 ohm

power transfer of cg structure
Power Transfer of CG Structure
  • Rs = RL = R = 50 ohm
  • S11=0, S21=1 @ Low frequency
summary cg structure
Summary – CG Structure
  • Noise performance
    • No extra resistive noise source
    • Independent of power consumption
  • Impedance matching
    • Broadband input matching
    • No passive components
  • Power consumption
    • gm=1/50
  • Power transfer
    • Independent of power consumption
inductor degeneration structure
Inductor Degeneration Structure

Zin

iout

Rs

Lg

Rs

Lg

iin

Cgs

Vgs

gmVgs

Vs

Vin

Ls

Vs

Ls

Zin

input matching for id structure
Input Matching for ID Structure

Zin

  • Zin=Rs
    • IM{Zin}=0
    • RE{Zin}=Rs

iout

Rs

Ls

Lg

Cgs

Vgs

gmVgs

gmLs/Cgs

Vs

effective transconductance
Effective Transconductance

Zin

iout

Rs

Ls

Lg

Cgs

Vgs

gmVgs

gmLs/Cgs

Vs

noise factor of id structure
Noise Factor of ID Structure
  • Calculate NF at w0

= 0 @ w0

input quality factor of id structure
Input Quality Factor of ID Structure

I

R

L

C

V

Rs

Ls

Lg

Cgs

gmLs/Cgs

Vs

noise factor of id structure42
Noise Factor of ID Structure
  • Increase power transfer

gmLs/Cgs = Rs

  • Decrease NF

gmLs/Cgs = 0

  • Conflict between
    • Power transfer
    • Noise performance
further discussion on nf
Further Discussion on NF
  • Frequency @ w0

w2 ~= 1/Cgs/(Lg+Ls)

  • Input impedance matched to Rs

RsCgs=gmLs

  • Suitable for hand calculation and design
  • Large Lg and small Ls
power transfer of id structure
Power Transfer of ID Structure
  • Rs = RL = R = 50 ohm
  • @
power consumption47
Power Consumption
  • Technology constant
    • L: minimum feature size
    • m: mobility, avoid mobility saturation region
  • Standard specification
    • Rs: source impedance
    • w0: carrier frequency
  • Circuit parameter
    • Lg, Ls: gate and source degeneration inductance
summary of id structure
Summary of ID Structure
  • Noise performance
    • No resistive noise source
    • Large Lg
  • Impedance matching
    • Matched at carrier frequency
    • Applicable to wideband application, S11<-10dB
  • Power transfer
    • Narrowband
    • Increase with gm
  • Power consumption
    • Large Lg
cascode
Cascode
  • Isolation to improve S12 @ high frequency
    • Small range at Vd1
    • Reduced feedback effect of Cgd
  • Improve noise performance

LL

Vo

Vbias

M2

Vd1

Rs

Lg

M1

Vs

Ls

slide50

Lg

Rs

Vo

Cgs

Vgs

gmVgs

Vs

Ls

LL

LL

Vo

Lg

Rs

M1

Vs

Ls

lna design example 1
LNA Design Example (1)

Vdd

Cb2

Lvdd

Lb2

Vout

M4

Output bias

Ld

Lout

Vbias

M3

M2

Lb1

Tm

Rs

M1

Lg

Lgnd

Cb1

Vs

Cm

Ls

Input bias

Off-chip matching

[3] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits,  vol. 32, pp. 745 – 759, May 1997.

lna design example 152
LNA Design Example (1)

Supply filtering

Lvdd

M4

Ld

Lout

Vbias

M3

M2

Lb1

Tm

Rs

M1

Lg

Lgnd

Cb1

Vs

Cm

Ls

Unwanted parasitics

[3] D. Shaeffer and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits,  vol. 32, pp. 745 – 759, May 1997.

circuit details
Circuit Details
  • Two-stage cascoded structure in 0.6 mm
  • First stage
    • W1 = 403 mm determined from NF
    • Ls accurate value, bondwire inductance
    • Ld = 7nH, resonating with cap at drain of M2
  • Second
    • 4.6 dB gain
    • W3 = 200 mm
lna design example 2
LNA Design Example (2)

NF = 1 + K/gmgm = gm1 + gm2

IB1

M2

Vout1

RB

NL

IREF

RX

M4

VB1

Off-chip matching

Ns

VRF

M1

M5

Cs

CX

Off-chip matching

M7

CB

M3

M6

[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996.

lna design example 257
LNA Design Example (2)

IB1

M8

M2

Vout1

RB

NL

IREF

RX

M4

VB1

Ns

VRF

M1

M5

Cs

CX

M7

CB

M3

M6

Bias feedback

[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996.

lna design example 258
LNA Design Example (2)

IB1

M8

M2

Vout1

RB

NL

IREF

RX

M4

VB1

Ns

VRF

M1

M5

Cs

CX

M7

CB

M3

M6

Bias feedback

[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996.

lna design example 259
LNA Design Example (2)

VA

IB1

M8

M2

Vout1

RB

NL

IREF

RX

M4

VB1

Ns

VRF

M1

M5

Cs

CX

M7

CB

M3

M6

Bias feedback

DC output = VB1

[4] A. Karanicolas, “A 2.7-V 900-MHz CMOS LNA and Mixer,” IEEE J. Solid-State Circuits, vol. 31, pp 1939 – 1944, Dec. 1996.

lna design example 3
LNA Design Example (3)
  • Objective is to design tunable RF LNA that would:
      • Operate over very wide frequency range with very fine selectivity
      • Achieve a good noise performance
      • Have a good linearity performance
      • Consume minimum power
lna architecture
LNA Architecture
  • The cascode architecture provides a good input – output isolation
  • Transistor M2 isolates the Miller capacitance
  • Input Impedance is obtained using the source degeneration inductor Ls
  • Gate inductor Lg sets the resonant frequency
  • The tuning granularity is achieved by the output matching network

VDD

R1

LD

M3

Matching Network

R2

M2

Output to Mixer

M1

LG

Input to LNA

LS

matching network
Matching Network
  • The output matching tuning network is composed of a varactor and an inductor.
  • The LC network is used to convert the load impedance into the input impedance of the subsequent stage.
  • A well designed matching network allows for a maximum power transfer to the load.
  • By varying the DC voltage applied to the varactor, the output frequency is tuned to a different frequency.
simulation results s11
Simulation Results - S11
  • The input return loss S11 is less than – 10dB at a frequency range between 1.4 GHz and 2GHz

Input return loss

simulation results nf
Simulation results - NF
  • The noise figure is 1.8 dB at 1.4 GHz and rises to 3.4 dB at 2 GHz.

Noise Figure

simulation results s22
Simulation Results - S22
  • By controlling the voltage applied to the varactor the output frequency is tuned by 2.5 MHz.
  • The output return loss at 1.77 GHz is – 44.73 dB and the output return loss at 1.7725 GHz – 45.69 dB.

S22 at 1.77 GHz

S22 at 1.7725 GHz

simulation results s2267
Simulation Results - S22
  • The output return loss at 2 GHz is – 26.47 dB and the output return loss at 1.9975 GHz – 26.6 dB.

S22 at 1.9975 GHz

S22 at 2 GHz

simulation results s21
Simulation Results - S21
  • The overall gain of the LNA is 12 dB

S21 at 1.4025 GHz

simulation results linearity
Simulation Results - Linearity
  • The third order input intercept is –3.16 dBm
  • -1 dB compression point ( the output level at which the actual gain departs from the theoretical gain) is –12 dBm

-1dB compression point

IIP3

from an earlier slide
From an earlier slide:
  • Flicker noise
    • Dominant at low frequency
  • Thermal noise
    • g: empirical constant

2/3 for long channel

much larger for short channel

    • PMOS has less thermal noise
  • Input-inferred noise

Vg

Id

Vi

Not accurate for low voltage short channel devices

modifications
Modifications

Thermonoise

g is called excess noise factor

= 2/3 in long channel

= 2 to 3 (or higher!) in short channel NMOS (less in PMOS)

fliker noise
Fliker noise
  • Traps at channel/oxide interface randomly capture/release carriers
    • Parameterized by Kf and n
      • Provided by fab (note n ≈ 1)
      • Currently: Kf of PMOS << Kf of NMOS due to buried channel
    • To minimize: want large area (high WL)
induced gate noise
Induced Gate Noise
  • Fluctuating channel potential couples capacitively into the gate terminal, causing a noise gate current
    • d is gate noise coefficient
      • Typically assumed to be 2g
    • Correlated to drain noise!
slide76

real

Input impedance

Set to be real and equal to source resistance:

output noise current
Output noise current

Noise scaling factor:

Where for 0.18 process

c=-j0.55, g=3, d=6, gdo=2gm,

d = 0.32

noise factor
Noise factor

Noise factor scaling coefficient:

Compare:

example
Example
  • Assume Rs = 50 Ohms, Q = 2, fo = 1.8 GHz, ft = 47.8 GHz
  • From
have we chosen the correct bias point
Have We Chosen the Correct Bias Point?

IIP3 is also a function of Q

if we choose vgs 1v
If we choose Vgs=1V
  • Idens = 175 mA/mm
  • From Cgs = 442 fF, W=274mm
  • Ibias = IdensW = 48 mA, too large!
  • Solution 1: lower Idens => lower power, lower fT, lower IIP3
  • Solution 2: lower W => lower power, lower Cgs, higher Q, higher NF
lower current density to 100
Lower current density to 100

Need to verify that IIP3 still OK (once we know Q)

lower current density to 10084
Lower current density to 100

We now need to re-plot the Noise Factor scaling coefficient

- Also plot over a wider range of Q

slide86

Recall

We previously chose Q = 2, let’s now choose Q = 6

- Cuts power dissipation by a factor of 3!

- New value of W is one third the old one

slide87
Rs = 50 Ohms, Q = 6, fo = 1.8 GHz, ft = 42.8 GHz
  • Ibias = IdensW =100mA/mm*91mm=9.1mA
  • Power = 9.1 * 1.8 = 16.4 mW
  • Noise factor scaling coeff = 10
  • Noise factor = 1+ wo/wt * 10

= 1+ 1.8G/42.8G *10 = 1.42

  • Noise figure = 10*log(1.42) = 1.52 dB
  • Cgs=442/3=147fF
  • Ldeg=Rs/wt=0.19nH
  • Lg=1/(wo^2Cgs) –Ldeg = 53 nH
other architectures of lnas
Other architectures of LNAs
  • Add output load to achieve voltage gain
  • In practice, use cascode to boost gain
    • Added benefit of removing Cgd effect
slide89

Differential LNA

Value of Ldeg is now much better controlled

Much less sensitivity to noise from other circuits

But: Twice the power as the single-ended version

Requires differential input at the chip

lna employing current re use
LNA Employing Current Re-Use
  • PMOS is biased using a current mirror
  • NMOS current adjusted to match the PMOS current
  • Note: not clear how the matching network is achieving a 50 Ohm match
    • Perhaps parasitic bondwire inductance is degenerating the PMOS or NMOS transistors?
slide91

Combining inductive degeneration and current reuse

Current reuse to save power

Larger area due to two degeneration

inductor if implemented on chip

NF: 2dB, Power gain: 17.5dB, IIP3: -

6dBm, Id: 8mA from 2.7V power supply

Can have differential version

F. Gatta, E. Sacchi, et al, “A 2-dB Noise Figure 900MHz Differential CMOS LNA,” IEEE JSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452

slide92

At DC, M1 and M2 are in cascode

At AC, M1 and M2 are in cascade

S of M2 is AC shorted

Gm of M1 and M2 are multiplied.

Same biasing current in M1 & M2

LIANG-HUI LI AND HUEY-RU CHUANG, MICROWAVE JOURNAL® from the February 2004 issue.

slide93

IM3 components in the drain current of the main transistor has the required information of its nonlinearity

  • Auxiliary circuit is used to tune the magnitude and phase of IM3 components
  • Addition of main and auxiliary transistor currents results in negligible IM3 components at output

Sivakumar Ganesan, Edgar Sánchez-sinencio, And Jose Silva-martinez

IEEE Transactions On Microwave Theory And Techniques, Vol. 54, No. 12, December 2006

slide94

MOS in weak inversion has speed problem

MOS transistor in weak inversion acts like bipolar

Bipolar available in TSMC 0.18 technology (not a parasitic BJT)

Why not using that bipolar transistor to improve linearity ?

slide95

Inter-stage Inductor gain boost

Inter-stage inductor with

parasitic capacitance form

impedance match network between

input stage and cascoded stage

boost gain lower noise figure.

Input match condition will be

affected

folded cascode
Folded cascode

Low supply voltage

Ld reduces or eliminates

Effect of Cgd1

Good fT

targeted specifications
Targeted Specifications
  • Frequency 2.4 GHz ISM Band
  • Noise Figure 1.6 dB
  • IIP3 -8 dBm
  • Voltage gain 20 dB
  • Power < 10mA from 1.8V
step 1 know your process
Step 1: Know your process
  • A 0.18um CMOS Process
  • Process related
    • tox = 4.1e-9 mm
    • e = 3.9*(8.85e-12) F/m
    • m = 3.274e-2 m^2/V.s
    • Vth = 0.52 V
  • Noise related
    • a = gm/gdo
    • d/g ~ 2
    • g ~ 3
    • c = -j0.55
insights
Insights:
  • gdo increases all the way with current density Iden
  • gm saturates when Iden larger than 120mA/mm
    • Velocity saturation, mobility degradation ---- short channel effects
    • Low gm/current efficiency
    • High linearity
  • a deviates from long channel value (1) with large Iden
insights103
Insights:
  • fT increases with Vod when Vod is small and saturates after Vod > 0.3V --- short channel effects
  • Cgs/W increases slowly after Vod > 0.2V
  • fT begins to degrade when Vod > 0.8V
    • gm saturates
    • Cgs increases
  • Should keep Vod ~0.2 to 0.4 V
obtain design guide plots104
Obtain design guide plots

knf vs input Q and current density

3-D plot for visual

inspection

2-D plots for

design reference

design trade offs
Design trade-offs
  • For fixed Iden, increasing Q will reduce the size of transistor thus reduce total power ---- noise figure will become larger
  • For fixed Q, reducing Iden will reduce power, but will increase noise factor
  • For large Iden, there is an optimal Q for minimum noise factor, but power may be too high
obtain design guide plots106
Obtain design guide plots

Linearity plots :IIP3 vs. gate overdrive and transistor size

insights107
Insights:
  • MOS transistor IIP3 only, when embedded into actual circuit:
    • Input Q will degrade IIP3
    • Non-linear memory effect will degrade IIP3
    • Output non-linearity will degrade IIP3
  • IIP3 is a very weak function of device size
  • Generally, large overdrive means large IIP3
    • But the relationship between IIP3 and gate overdrive is not monotonic
    • There is a local maxima around 0.1V overdrive
step 4 estimate f t
Step 4: Estimate fT

Small current budget ( < 10mA )

does not allow large gate over drive :

Vod ~ 0.2 V ~ 0.4 V

fT ~ 40 ~ 44 GHz

step 4 determine i den q and calculate device size
Step 4: Determine Iden, Q andCalculate Device Size

Gm/W~0.4

Select Iden = 70 mA/mm, =>Vod~0.23V

slide110

If Q = 4, IIP3 will have enough margin:

Estimated IIP3:

IIP3(from curve) – 20log(Q) = 8-12 = -4dBm

Specs require: -8 dBm

slide111

Q=4 and Iden = 70mA/mm meet the

noise factor requirement

slide112

Gm=0.4*128 ~ 50 mS

fT = gm/(Cgs*2pi) = 48 GHz