332:578 Deep Submicron VLSI Design Lecture 19 Advanced Testing

1. 332:578 Deep SubmicronVLSI DesignLecture 19 Advanced Testing • Schmoo Plots • Automatic Test Equipment • Additional JTAG Instructions • Summary Michael Bushnell and David Harris Rutgers U. and Harvey Mudd College Deep Submicron VLSI Des. Lec. 19

2. Source: “Essentials of Testing for Logic, Memory, and Mixed-Signal Circuits” by Bushnell & Agrawal, Springer, 2000 Deep Submicron VLSI Des. Lec. 19

3. Shmoo Plots • How to diagnose failures? • Hard to access chips • Picoprobes • Electron beam • Laser voltage probing • Built-in self-test • Shmoo plots • Vary voltage, frequency • Look for cause of electrical failures Deep Submicron VLSI Des. Lec. 19

4. Manufacturing Test • A speck of dust on a wafer is sufficient to kill chip • Yield of any chip is < 100% • Must test chips after manufacturing before delivery to customers to only ship good parts • Manufacturing testers are very expensive • Minimize time on tester • Careful selection of test vectors Deep Submicron VLSI Des. Lec. 19

5. Testing Your Chips • If you don’t have a multimillion dollar tester: • Build a breadboard with LED’s and switches • Hook up a logic analyzer and pattern generator • Or use a low-cost functional chip tester Deep Submicron VLSI Des. Lec. 19

6. TestosterICs • Ex: TestosterICs functional chip tester • Designed by clinic teams and David Diaz at HMC • Reads your IRSIM test vectors, applies them to your chip, and reports assertion failures Deep Submicron VLSI Des. Lec. 19

7. Automatic Test Equipment Components • Consists of: • Powerful computer • Powerful 32-bit Digital Signal Processor (DSP) for analog testing • Test Program (written in high-level language) running on the computer • Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) • Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad) Deep Submicron VLSI Des. Lec. 19

8. ADVANTEST Model T6682 ATE Deep Submicron VLSI Des. Lec. 19

9. Additional JTAG Instructions Deep Submicron VLSI Des. Lec. 19

10. CLAMP Instruction • Purpose: Forces component output signals to be driven by boundary-scan register • Bypasses the boundary scan chain by using the one-bit Bypass Register • Optional instruction • May have to add RESET hardware to control on-chip logic so that it does not get damaged (by shorting 0’s and 1’s onto an internal bus, etc.) Deep Submicron VLSI Des. Lec. 19

11. HIGHZ Instruction • Purpose: Puts all component output pin signals into high-impedance state • Control chip logic to avoid damage in this mode • May have to reset component after HIGHZ runs • Optional instruction Deep Submicron VLSI Des. Lec. 19

12. BYPASS Instruction • Purpose: Bypasses scan chain with 1-bit register Deep Submicron VLSI Des. Lec. 19

13. Summary • Schmoo Plots – Useful for improving chip yield • Automatic Test Equipment – essential for testing chips • Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. • Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. Deep Submicron VLSI Des. Lec. 19