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MIPS Architecture

MIPS Architecture. CPSC 321 Computer Architecture Andreas Klappenecker . MIPS Design Paradigms. Simplicity favors regularity all instructions single size three register operands in arithmetic instr. keep register fields in the same place Smaller is faster 32 registers

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MIPS Architecture

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  1. MIPS Architecture CPSC 321 Computer Architecture Andreas Klappenecker

  2. MIPS Design Paradigms • Simplicity favors regularity • all instructions single size • three register operands in arithmetic instr. • keep register fields in the same place • Smaller is faster • 32 registers • Make good compromises • large addresses and constants versus unique instruction length • Make the common case fast • PC-relative addressing for conditional branches

  3. Basic Functional Components • Control unit • Register file • Arithmetic logic unit (ALU) • Program counter (PC) • Memory • Instruction register (IR)

  4. Simplified Datapath Diagram Program Counter (PC) Memory Instruction Register ALU Rs Control Address Logic Rt Rd 4 Data In Register File

  5. MIPS R2000 • Several firsts: • First RISC microprocessor • First microprocessor to provide integrated support for instruction & data cache • First pipelined microprocessor (sustains 1 instruction/clock) • Implemented in 1985 • 125,000 transistors • 5-8 MIPS

  6. Number Value Name Registers return values from functions pass parameters to functions $t0-$t7 are caller saved registers – use these registers in functions $s0-$s7 are callee-saved registers – use these registers for values that must be maintained across function calls.

  7. Instruction Word Formats Register format Immediate format Jump format op-code rs rt rd shamt funct 6 5 5 5 5 6 op-code rs rt immediate value 6 5 5 16 op-code 26 bit current segment address 6 26

  8. Register Format (R-Format) Register format op: basic operation of instruction funct: variant of instruction rs: first register source operand rt: second register source operand rd: register destination operand shamt: shift amount op-code rs rt rd shamt funct 6 5 5 5 5 6

  9. R-Format Example Register format (op, funct)=(0,32): add rs=17: first source operand is $s1 rt=18: second source operand is $s2 Rd=8: register destination is $t0 add $t0, $s1, $s2 0 17 18 8 0 32 6 5 5 5 5 6

  10. Immediate Format (I-Format) Immediate format op determines the instruction rs is the source register rt is the destination register 16bit immediate value op rs rt immediate value 6 5 5 16

  11. I-Format Example Immediate format op=8 means addi rs=29 means source register is $sp rt=29 means $sp is destination register immediate value = 4 addi $sp, $sp, 4 8 29 29 4 6 5 5 16

  12. How can we load a 32bit constant? • How can we load $s0 with • 0000 0000 0011 1101 0000 1001 0000 0000 • Load upper 16bits with • lui $s0, Ox003d so that $s0 contains • 0000 0000 0011 1101 0000 0000 0000 0000 • Add immediate 16bit value to complete load • addi $s0, $s0, 0x0900 so that $s0 contains value • 0000 0000 0011 1101 0000 1001 0000 0000

  13. MIPS Addressing Modes • Register addressing • Base displacement addressing • Immediate addressing • PC-relative addressing • address is the sum of the PC and a constant in the instruction • Pseudo-direct addressing • jump address is 26bits of instruction concatenated with upper bits of PC

  14. What next? • Details of the arithmetic logic unit • Chapter 4 • Project: Build your own ALU • Details of datapath and control • Chapter 5 • Project: Build your own CPU • Pipelining • Caching

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