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Develop a Verilog program for a pipelined CPU including key instructions and hazard handling units. Implement forwarding unit and stall cycles resolution for data and control hazards. Create code, test bench, clock signal, and output mechanisms as per requirements.
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CA 2007Project 1– Pipelined CPU using Verilog – Yeh-Juin Lin (林業峻) d95027@csie.ntu.edu.tw 5/14 2007
Project 1 – Pipelined CPU using Verilog – • Write a Verilog behavior Pipelined Cycle CPU program • Required Instruction Set： • and • or • add • sub • mul • lw • sw • beq • j • addi
Requirement • Register File：32 Registers • Data Memory：32 Bytes • Data Path & Module Name • (In page 6) • MUL OpCode： • Hazard handling • Data hazard: • implement the Forwarding Unit to reduce or avoid the stall cycles. • The data dependency instruction follow “lw” must stall 1 cycle. • Control hazard: • Branch result must be find in ID stage. • The instruction follow ‘beq’ or ‘j’ instruction must stall 1 cycle.
Requirement (Cont’d) • Source code (put all .v file into “code” directory) • TestBench (Design by yourself~!) • Initialize storage units • Load instruction.txt into instruction memory • Create clock signal • Output cycle count in each cycle • Output Register File & Data Memory in each cycle • Print result to output.txt • Report (project1_teamXX.doc) • Members & Team Work • How do you implement this Pipelined CPU. • How do you implement the TestBench. • Problems and solution of this project. • Put all files and directory into project1_teamXX.rar
Due Date • Deadline: • Deadline: 6/4 (3 weeks) • Before the Project • Team work, 3 persons at most • Please reply the title about ” Project分組” in the forum. • Must include student ID and student name.
