UNIT 8

1. UNIT 8 Introduction to buses

2. Introduction • To interconnect memories,I/O devices,and other sections of a computer, most often a bus is used.

3. “CPU bus” or “System bus” “Bus interface” “I/O bus” CPU-Memory-I/O Architecture Memory CPU I/O module I/O device

4. Buses – Common Characteristics • Multiple devices communicating over a single set of wires • Only one device can talk at a time or the message is garbled • Each line or wire of a bus can at any one time contain a single binary digit. Over time, however, a sequence of binary digits may be transferred • These lines may and often do send information in parallel • A computer system may contain a number of different buses

5. Interfacing Buses • The primary disadvantage of using a large number of individual cables to interconnect parts of a system are cost and complexity. • A widely used technique to interface modules efficiently at low cost employs a single bus to interconnect all the units.(Fig. 8.8) • Here, the several lines or conductors which form the bus pass through and connect to a number of units,or modules. • The bus interface is usually standardized since the same bus connects all the units • In such case where each unit connects only once to the bus, the amount of interface circuitry and logic required tends to be lower than for separate connections between units.

6. Interfacing Buses • Modules which are bused together share the same data lines. • It is necessary for each module to be able to both write onto and read from a given line. • To share lines on a bus , a logic circuit called a three-state or tristate driver is used.

7. Three state driver operation Refer page 388 for explanation

8. Three state driver operation • Three state drivers are widely used in the interfaces for buses. • They enable control of bus lines to pass from interface to interface as is appropriate.

9. Octal latches with tristate drivers • The fig shows a tristate octal D-Type latch IC package with eight latches equipped with tristate drivers. • Each latch reads the input at D when the clock input is high • The outputs from the latches are forced on the outputs from the chip when the ENABLE is a 1.

10. Octal Flip Flop Chip with Tristate Drivers • The figure shows an octal tristate buffer with negative edge triggered flipflops in which the outputs are forced to the input state only when the ENABLE input is high (a 1) • Several units are sharing the same bus lines • Two modules do not attempt to write data on the bus at the same time

11. Bus Formats & Operation • A number of different types and several different standards for buses exist. • All buses can be divided into three major sections • Address • Data • Control Section • Fig 8.12 shows the three sections using a wide, ribbonlike representations for the multiple lines (wires) • Fig 8.12 b shows that sometimes a single printed line is used with a starting slash thru the printed line to indicate that there are actually a number of lines (wires) • Both representations are frequently used

12. Bus Formats & Operation

13. Bus Formats & Operation • Most buses use tristate drivers to write data on the data lines • The address lines are completely controlled by the bus master • Bus Master is generally a mini/micro processor CPU • In case of single bus master the remaining devices connected to the bus are called slaves • Each slave has an address number and the bus master uses the address lines to control who is to use the bus • In some systems, devices other than the CPU can take control of the bus and controlling device is called the bus master only when it has control and at that time the responding devices are called slaves • In some cases more than one device can take control of the bus and the address lines also are driven by tristate drivers

14. Bus Formats & Operation • Buses transfer information over data wires by using either a synchronous or asynchronous techniques • Synchronous – Assume a CPU wishes to read & write from peripheral device, then each device is given a separate number and a device is selected by the CPU placing that number on the address line Fig 8.13 shows the timing of synchronous transfers involving a set of address wires, data wire and a READ & WRITE control line • The CPU places the number of the device to be read from, on the address line and lowers the READ line and the selected device must place data on the DATA line which means enabling its tristate drivers connected to the bus DATA wires

15. Bus Formats & Operation

16. Bus Formats & Operation • The device being written into or read from must respond during the fixed time period permanently established by the CPU • If a READ is performed, the device must place data on the data line at once and keep them there while the READ line is down • For a WRITE, the device must have already read the data by the time that the WRITE line goes high • Advantages • Synchronous transfers are thought to be the fastest way to transfer data • It is used for memory data transfers and sometimes for transferring data to other types of devices • Drawbacks • All devices must be able to respond at the same speed unless the CPU has READ & WRITE signals of different duration for different devices • To overcome this problem asynchronous transfer technique is used

17. Bus Formats & Operation • Another control line is required called DATA VALID or RECEIVED when an asynchronous bus transfer technique is used (Fig 8.14)

18. Bus Formats & Operation • This line is controlled by the devices and not the CPU • A tristate driver will be required for each device using this line if there is more than one device on the bus • Timing Sequence - To read from the bus, the CPU sets the number of the device on the ADDRESS line and lowers the READ line - Selected device place data on the DATA lines and a 1 on the DATA VALID or RECEIVED line - If the device is slow in preparing its data, the CPU must wait until the data are on the DATA line - Then the DATA VALID of RECEIVED line is erased - Now the CPU reads the data and raises the lowered READ line to a 1 • The selected device must keep its data on the DATA line until READ goes to a 1 • The selected device then turns off its tristate drivers to the DATA lines and lowers the DATA VALID or RECEIVED lines • A write operation is performed similarly

19. Bus Formats & Operation • The asynchronous procedure involves hand shake • This is how fast & slow devices can be accommodated on the same bus which is the reason for the wide use of asynchronous buses

20. Handshake : Agreement between two independent units 1) Source-initiated handshake : 2) Destination-initiated handshake : Timeout : If the return handshake signal does not respond within a given time period, the unit assumes that an error has occurred.       Source-initiated handshake Destination-initiated handshake