Unit - 2

1. Unit - 2 Bus Cycles and Memory Organization

2. Contents: • Initialization and configuration • Bus operations – Reset • Non pipelined and pipelined ( read & write cycles) • Memory organization & I/O organization • Data transfer mechanism – 8,16,32 bit Data bus interface • Pentium programmers model • Register set • Addressing modes • Data Types & BUS cycle.

3. Memory Organization

4. I/O Organization

5. I/O Organization

6. Reset Operation: • Reset signal is input signal • Purpose - Initialize its register to its known state - Invalidate the code & data cache - Fetch its first instruction from memory

7. If Reset signal = activated then Pentium processor enter into BIST • Test result is stored in EAX register • If test is correct, EAX=0 • Types:

8. Table: State of Pentium after a Reset

9. Activity after reset start Is ERROR=0? N Fetch instruction from FFFFFFF0h Initialize registers Is Busy=1? N Y Y Perform Self Test Set ET=1 Update EAX Self Test Fail Is EAX=0? N Self Test Pass Set DH=03H

10. Non-Pipelined Read Cycle

11. Non-Pipelined Write Cycle

12. Pipelined Read-Write Cycle

13. Bus Operations: Reset, Bus cycle • Bus (definition) • Types • Address bus • Data bus • Control bus

14. Burst Cycle

15. Table: Burst transfer Order 1st 2nd 3rd 4th Address address address address ------------------------------------------------ 0 8 10 18 8 0 18 10 10 18 0 8 18 10 8 0 -------------------------------------------------

16. Pentium programmers model:

17. General Purpose Registers:

18. Control registers

19. Debug Register