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Flip-Flops and Related Devices. Chapter 8. S-R (SET-RESET) Latch. Active-HIGH input Active-LOW input S-R Latch S’-R’ Latch. S-R (SET-RESET) Latch. S-R Latch Logic Symbol. Switch Contact De-bounce. Figure 8--6 . When the set is high and reset is low Q is high and Q’ is low.

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s r set reset latch
S-R (SET-RESET) Latch

Active-HIGH input Active-LOW input

S-R Latch S’-R’ Latch

s r flip flop truth table for nor flip flop
S-R flip flop truth table for NOR flip-flop

S R Q Q’

0 0 Q Q’ hold condition

1 0 1 0 set

0 1 0 1 reset

1 1 0 0 not allowed

s r flip flop using nands
S-R flip flop using NANDs

Set high reset low Q high Q’ low

s r flip flop truth table for nand flip flop
S-R flip flop truth table for NAND flip-flop

S R Q Q’

0 0 Q Q’ hold condition

1 0 1 0 set

0 1 0 1 reset

1 1 1 1 not allowed

slide17

S-R flip flops do not come ready made but a 7402 dual 2input NOR came be used to make the S-R flip flops

slide18

Gated SR Latch

  • A gate input is added to the S-R flip-flop to make the flip-flop synchronous.
  • In order for the set and reset inputs to change the flip-flop, the gate input must be active (high).
  • When the gate input is low, the flip-flop remains in the hold condition.
slide21

When the gate is high

The flip flop works

truth table for s r gated flip flop
Truth Table for S-R gated Flip Flop

S R G Q Q’

0 0 0 Q Q’ Hold

1 0 0 Q Q’ Hold

0 1 0 Q Q’ Hold

1 1 0 Q Q’ hold

0 0 1 Q Q’ hold

1 0 1 1 0 set

0 1 1 0 1 reset

1 1 1 0 0 not allowed

slide23

Gated D Latch

  • The D (data) flip-flop has a single input that is used to set and to reset the flip-flop.
  • When the gate is high, the Q output will follow the D input.
  • When the gate is low, the flip-flop is latched.
slide26

The J-K flip-flop has a toggle mode of operation when both J and K inputs are high.Toggle means that the Q output will change states on each active clock edge.

J, K and Cp are all synchronous inputs.

The master-slave flip-flop is constructed with two latches. The master latch is loaded with the condition of the J-K inputs while the clock is high. When the clock goes low, the slave takes on the state of the master and the master is latched.

The master-slave is a level-triggered device.

The master-slave can interpret unwanted signals on the J-K inputs.

slide33

I would love to show this circuit Toggle but it will not since the Mater S-R flip flop is seeing a not allowed 1 1 input and putting out a 0 at Q and Q’ both.

truth table for j k flip flop
Truth Table for J-K Flip Flop

J K Q

0 0 Q Hold

1 0 1 Set

0 1 0 Reset

1 1 Q’ Toggle

slide36

The edge-triggered J-K will only accept the J and K inputs during the active edge of the clock.

The small triangle on the clock input indicates that the device is edge-triggered.

A bubble on the clock input indicates that the device responds to the negative edge. no bubble would indicate a positive edge-triggered device.

slide38

Toggle

Toggle

Remain the same

Reset

Reset

flip flop operating characteristics
Flip-Flop Operating Characteristics
  • Propagation Delay Times
  • Set-up Time
  • Hold Time
  • Maximum Clock Frequency
  • Pulse Width
  • Power Dissipation
propagation delay
Propagation Delay
  • Clk to Output Q
  • Preset’ and CLR’ to Output Q
setup time and hold time
Setup Time and Hold Time
  • Setup Time
  • Hold Time
flip flop applications
Flip-Flop Applications
  • Parallel Data Storage
  • Frequency Division
  • Counting
slide47

A race condition occurs when the data inputs (J-K or D) to a flip-flop are changing at the same time as the active clock transition.

The top J-K Flip Flop should not work due to a race condition

The bottom J-K flip flop should work

slide48

Top Flip Flop

Top Clock

Bottom Flip Flop

Bottom delayed clock

slide49

Set-up time is the time that the data inputs to a flip-flop

must be set before the active clock transition.

20ns of set up time is required for the J-K flip flop to accept the high at K

slide50

Hold time is the amount of time that the data inputs must maintain their level after active clock transition.

The clock in blue is after the active K in red the flip flop will not work

slide51

The clock is in red.

The K input is in blue

Note the 26 ns hold time

slide52

The time required for the Q output to change as a result of some input is called the propagation delay.

    • tPLH is the propagation delay when the Q output goes from low to high.

I see 7.7ns for tPLH

slide53

tPHL is the propagation delay when the Q output goes from high to low.

I see 7.6ns for tPHL since the blue is the output and the red is the clock

slide54

The propagation delay can be caused by an asynchronous input (RD or SD) or a synchronous input (Cp).

The output Q goes low with the clock not shown. The out put goes high due to a preset note the 10ns tPLH caused by the preset

slide55

There are several other parameters that will also be listed in a manufacturers data sheet.

        • Maximum frequency (Fmax) - The maximum frequency allowed at the clock input.
        • Clock pulse width (LOW) [tW(L)] - The minimum width that is allowed at the clock input during the LOW level.
        • Clock pulse width (HIGH) [tW(H)] - The minimum width that is allowed at the clock input during the high level.
        • Set or Reset pulse width (LOW) [tw(L)] - The minimum width of the LOW pulse at the set or reset inputs.
basic operation of a 555 timer
Basic Operation of a 555 Timer
  • Threshold
  • Control Voltage
  • Trigger
  • Discharge
  • Reset
  • Output
555 timer as a one shot
555 Timer as a One Shot

tw = 1.1R1C1 = 1.1(2000)(1F) = 2.2ms

astable operation of 555 timer
Astable operation of 555 Timer

tH = .7 (R1+R2)C1 =2.1ms tL = .7R2C1 = 0.7ms

registered logic in programmable logic devices
Registered Logic inProgrammable Logic Devices
  • Registered refers to the use of a flip-flop
  • The flip-flop is used to store the result of a logic function
  • The flip-flop may be a D flip-flop of be programmable to operate as a J-K of S-R flip-flop
slide70

Generic CPLD/FPGA

Registered Logic

select elements
Select Elements
  • Are multiplexers or data selectors
  • They are programmed to pass one input
  • They will have 2 or more inputs FF control select can be programmed to pass the combinational output function or another control signal to the FF input
  • Register bypass can be programmed to
    • Route the output of the combinational generator to an output
    • Route the output of the combinational generator to an interconnect
    • Store it in the flip-flop
select elements1
Select Elements

Combinational

Registered

latches and flip flops using vhdl
Latches and Flip-flops Using VHDL
  • The S-R latch can be either high or low inputs
  • Q and QNOT are both inputs and outputs, VHDL has a bi-directional mode inout which is used in the port statement

port( S, R: in std_logic; Q, Qnot: inout std_logic);

s r latch in vhdl
S-R Latch in VHDL

library ieee;

use ieee.std_logic_1164.all;

entity SRlatch is

port( S, R: in std_logic; Q, Qnot: inout std_logic);

end entity SRlatch

s r latch in vhdl continued
S-R Latch in VHDL Continued

architecture Latch_Operation of SRlatch is

begin

process(S,R) is

begin

Q <= Qnot nor S;

Qnot <= Q nor R;

end process;

end architecture Latch_Operation

s r latch to s r flip flop
S-R Latch to S-R Flip-flop
  • The S-R flip-flop may use a clock pulse
  • The clock pulse needs to be an edge trigger event
  • Using the VHDL statement wait until rising_edge (clock) will cause the program to be driven by the the clock
  • Use the statement falling_edge for negative edge triggered
s r flip flop in vhdl example 8 16
S-R Flip-flop in VHDL Example 8-16

library ieee;

use ieee.std_logic_1164.all;

entity SRFlipFlop is

port( S, R, Clock: in std_logic; Q, Qnot: inout std_logic);

end entity SRFlipFlop

s r flip flop in vhdl example 8 161
S-R Flip-flop in VHDL Example 8-16

architecture FlipFlopBehavior of SRFlipFlop is

begin

process (S, R, Clock) is

begin

wait until rising_edge (Clock);

if S=‘1’ and R=‘0’ then

Q <=‘1’;

elseif S=‘0’ and R=‘1’ then

Q <=‘0’;

else

Q <=Q;

end if;

Qnot <= not Q;

end process;

end architecture FlipFlopBehavior;

j k flip flop in vhdl example 8 17
J-K Flip-flop in VHDL Example 8-17

J K Q

0 0 Q Hold

1 0 1 Set

0 1 0 Reset

1 1 Q’ Toggle

library ieee;

use ieee.std_logic_1164.all;

entity JKFlipFlop is

port( J, K, Clock: in std_logic; Q, Qnot: inout std_logic);

end entity JKFlipFlop

j k flip flop in vhdl example 8 171
J-K Flip-flop in VHDL Example 8-17

architecture FlipFlopBehavior of JKFlipFlop is

begin

process (J, K, Clock) is

begin

wait until rising_edge (Clock);

if J=‘1’ and K=‘0’ then

Q <=‘1’;

elseif J=‘0’ and K=‘1’ then

Q <=‘0’;

elseif J=‘1’ and K=‘1’ then

Q <=Qnot;

else

Q<=Q;

end if;

Qnot <= not Q;

end process;

end architecture FlipFlopBehavior;

d flip flop
D Flip-Flop
  • Use the S-R flip-flop and and an inverter
d flip flop vhdl code
D-Flip-Flop VHDL code

library ieee;

use ieee.std_logic_1164.all;

entity D_flip_flop is

port( D, Clock: in std_logic; Q, Qnot: inout std_logic);

end entity D_flip_flop

d flip flop vhdl code continued
D-Flip-Flop VHDL Code continued

architecture Flip_Flop_Behavior of D_flip_flop is

begin

process(D, Clock) is

begin

wait until rising_edge (clock);

if D = ‘1’ then

Q <= ‘1’;

else

Q <= ‘0’;

end if

Qnot <= not Q

end process;

end architecture Flip_Flop_Behavior

re usable packages
Re-usable Packages
  • Make S-R latch a package and use it many times
  • Using a VHDL package allows the use of the S-R latch in the construction of other logic devices

library ieee;

use ieee.std_logic_1164.all;

package SRPackage is

procedure ActiveLowSRlatch ( Snot, Rnot: in std_logic; Q, Qnot: inout std_logic);

end entity SRPackage;

re usable packages1
Re-usable Packages

package body SRPackage is

procedure ActiveLowSRlatch (Snot, Rnot: in std_logic; Q, Qnot: inout std_logic) is

begin

if Snot = ‘1’ and Rnot=‘0’ then

Q :=‘0’; Qnot:=‘1’;

elseif Snot=‘0’ and Rnot=‘1’ then

Q:=‘1’; Qnot:=‘0’;

elseif Snot=‘0’ and Rnot=‘0’ then

Q:=Qnot; Qnot := not Q

end if;

end ActiveLowSRlatch;

end SRPackage;

re usable packages example 8 18
Re-usable Packages Example 8-18
  • Active Low JK flip-flop with positive edge using SRPackage
  • Library work

library ieee, work;

use ieee.std_logic_1164.all;

use work.SRPackage.all;

entity ActiveLowJK is

port ( Jnot, Knot, clock: in std_logic; X, Y: out std_logic);

end entity ActiveLowJK;

re usable packages example 8 181
Re-usable Packages Example 8-18

architecture JKBehavior of ActiveLowJK is

begin

process (Jnot, Knot)

variable V1, V2: std_logic;

begin

wait until rising_edge (clock);

FF1:ActiveLowSRlatch (Snot=>Jnot, Rnot=>Knot, Q=>V1, Qnot=>V2);

X<=V1; Y<=V2;

end process;

end architecture JKBehavior;

j k flip flop components
J-K Flip-Flop Components
  • In Example 8-17 a a modified S-R latch package was used to define the J-K flip-flop
  • The J-K flip-flop will be made into a component for used in a frequency divider

component JKFlipFlop is

port( J,K,Clock: in std_logic; Q, Qnot: inout std_logic);

end component JKFlipFlop;

vhdl keyword buffer
VHDL Keyword buffer
  • Similar to in, out, and inout used in a port statement
  • buffer is unidirectional

port(clock: in std_logic; Qa, Qb, Fout: buffer std_logic);

component and buffer in vhdl example 8 19
Component and Buffer in VHDL Example 8-19

library ieee;

use ieee.std_logic_1164.all;

entity FreqDivider is

port ( clock: in std_logic; Qa, Qb, Fout: buffer std_logic);

end entity FreqDivider;

component and buffer in vhdl example 8 191
Component and Buffer in VHDL Example 8-19

architecture FreqDivBehavior of FreqDivider is

component JKFlipFlop is

port (J, K, Clock: in std_logic; Q: inout std_logic);

end component JKFlipFlop;

signal I: std_logic;

begin

I<=‘1’;

FFA: JKFlipFlop port map (J=>I, K=>I, Clock=>clock, Q=>Qa);

FFB: JKFlipFlop port map (J=>I, K=>I, Clock=>Qa, Q=>Qb);

FFC: JKFlipFlop port map (J=>I, K=>I, Clock=>Qb, Q=>Fout);

end architecture FreqDivBehavior;

vhdl software
VHDL Software
  • Use working code to make more complex code
  • Complex operations can often be better described using the behavioral approach
  • The VHDL complier will decide how to implement the code and will know from the program statements whether it will be registered or combinational
  • This allows the code to be usable on other programmable devices
counters

Counters

Chapter 9

2 bit asynchronous counter1
2-Bit Asynchronous Counter

Clock

Q0

Q0(LSB)

Q1(MSB)

asynchronous decade counter
Asynchronous Decade Counter
  • The modulus of a counter is the number of unique states that the counter will sequence through.
  • The maximum modulus is 2n where n is the number of flip-flops.
up down synchronous counters
Up/Down Synchronous Counters

CLK

Q0

Q1

Q2

UP/Down’

2 bit asynchronous binary counter using vhdl
2-bit Asynchronous Binary Counter Using VHDL

The clock will be input C.

FF0 the first Flip-flop

FF1 the second flip-flop

slide118

2-bit Asynchronous Binary Counter Using VHDL

entity TwoBitCounter is

port(clock: in std_logic; Qa, Qb: buffer std_logic);

end entity TwoBitCounter;

architecture CounterBehavior of TwoBitCounter is

component JKFlipFlop is

port( J, K, Clock: in std_logic; Q, Qnot: inout std_logic);

end component JKFlipFlop;

slide119

2-bit Asynchronous Binary Counter Using VHDL

signal I: std_logic;

begin

I <= ‘1’;

FF0:JKFlipFlop port map (J=>I, K=>I, Clock =>clock, Qnot=>Qnot, Q=>Qa);

FF1:JKFlipFlop port map (J=>I, K=>I, Clock=>Qnot, Q=>Qb);

end architecture CounterBehavior;

asynchronous truncated counters
Asynchronous Truncated Counters

To truncate a counter a clear function must be added to the J-K flip-flop

component JKFlipFlopClear is

port( J, K, Clock, Clr: in std_logic; Q, Qnot: inout std_logic);

end component JKFlipFlopClear

asynchronous truncated counters example 9 11
Asynchronous Truncated Counters Example 9-11

Asynchronous MOD6 (0,1,..5) JK flip-flop with clear

library ieee;

use ieee.std_logic_1164.all;

entity ModSixCounter is

port(clock: in std_logic; Clr: in std_logic; Q0, Q1, Q2: buffer std_logic);

end entity ModSixCounter;

asynchronous truncated counters example 9 111
Asynchronous Truncated Counters Example 9-11

architecture CounterBehavior of ModSixCounter is

signal Clear: std_logic;

component JKFlipFlopClear is

port (J, K, Clr, Clock: in std_logic; Q, Qnot: inout std_logic);

end component JKFlipFlopClear;

signal I: std_logic;

begin

I <= ‘1’; Clear <= not (Q1 and Q2);

FF0: JKFlipFlopClear port map (J=>I, K=>I, Clr=>Clear, Clock =>clock, Q=>Q0);

FF1: JKFlipFlopClear port map (J=>I, K=>I, Clr=>Clear, Clock=>Q0, Q=>Q1);

FF2: JKFlipFlopClear port map (J=>I, K=>I, Clr=>Clear, Clock=>Q1, Q=>Q2);

end architecture CounterBehavior;

synchronous counters in vhdl
Synchronous Counters in VHDL
  • Synchronous refers to events that occur simultaneously
  • For synchronous counters all flip-flops are clocked at the same time using the same clock pulse
  • An example in VHDL would be to use the J-K flip-flop defined as a component then have it clocked using the same clock pulse

Figure 9-13

slide124

Synchronous Counters in VHDL

entity FourBitSyncCounter is

port( I, clock: in std_logic; Q0, Q1, Q2, Q3: buffer std_logic);

end entity FourBitSyncCounter

architecture CounterBehavior of FourBitSyncCounter is

signal S0, S1, S2: std_logic;

component JKFlipFlop is

port(J, K, Clock: in std_logic;Q, Qnot inout std_logic);

end component JKFlipFlop

slide125

Synchronous Counters in VHDL

begin

FF0: JKFlipFlop port map (J=>I, K=>I, Clock=>clock, Q=>Q0);

S0<= Q0;

FF1: JKFlipFlop port map (J=>S0, K=>S0, Clock=>clock, Q=>Q1);

S1 <= Q0 and Q1;

FF2: JKFlipFlop port map (J=>S1, K=>S1, Clock=>clock, Q=>Q2);

S2 <= Q0 and Q1 and Q2;

FF3: JKFlipFlop port map (J=>S2, K=>S2, Clock=>clock, Q=>Q3);

end architecture CounterBehavior

slide127

3-Bit Gray Code CounterExample 9-13

library ieee;

use ieee.std_logic_1164.all;

entity StateCounter is

port(clock: in std_logic; Q: buffer std_logic_vector(0 to 2) );

end entity StateCounter;

slide128

3-Bit Gray Code CounterExample 9-13

architecture CounterBehavior of StateCounter is

begin

process (Clock)

begin

if Clock = ‘1’ and Clock’ event then

case Q is

when “000” => Q <= “010”;

when “010” => Q <= “110”;

when “110” => Q <= “100”;

when “100” => Q <= “101”;

when “101” => Q <= “001”;

when “001” => Q <= “000”;

when others => Q <= “000”;

end case;

end if;

end process;

end architecture CounterBehavior;

shift registers

Shift Registers

Chapter 10

basic shift register functions
Basic Shift Register Functions
  • Data Storage
  • Data Movement
  • D flip-flops are use to store and move data
serial in parallel out shift registers
Serial in/Parallel out shift registers

After 4 clock pulses, 0110

timing diagram for 8 bit serial in parallel out
Timing Diagram for 8-bit Serial in/Parallel Out

CLR’

Data In

QA

QB

QC

QD

QE

QF

QG

QH

CLK

timing diagram for 8 bit parallel load shift resister
Timing Diagram for 8-bit Parallel Load Shift Resister

Loaded

10101010

Output

10101010

Shift/Load’

Output

D0

D1

D2

D3

D4

D5

D6

D7

CLK

bidirectional shift registers
Bidirectional Shift Registers
  • Data can be shifted left
  • Data can be shifted right
  • A parallel load maybe possible
  • 74HC194 is an bidirectional universal shift register
74194 data table
74194 data table

_____ | MODE | | SERIAL | PARALLEL | OUTPUTS

CLEAR | S1 S0 | CLK | LEFT RIGHT | A B C D | QA QB QC QD

-----------|----------|--------|--------------------|-----------------------|------------------

0 | X X | X | X X | X X X X | 0 0 0 0

1 | X X | 0 | X X | X X X X | QA0 QB0 QC0 QD0

1 | 1 1 | POS | X X | a b c d | a b c d

1 | 0 1 | POS | X 1 | X X X X | 1 QAn QBn QCn

1 | 0 1 | POS | X 0 | X X X X | 0 QAn QBn QCn

1 | 1 0 | POS | 1 X | X X X X | QBn QCn QDn 1

1 | 1 0 | POS | 0 X | X X X X | QBn QCn QDn 0

1 | 0 0 | X | X X | X X X X | QA0 QB0 QC0 QD0

74194 parallel load
74194 parallel load

CLR’

S1

S0

QA

QB

QC

QD

SR

SL

A

B

C

D

CLK

74194 shift right
74194 shift right

CLR’

S1

S0

QA

QB

QC

QD

SR

SL

A

B

C

D

CLK

74194 shift left
74194 shift left

CLR’

S1

S0

QA

QB

QC

QD

SR

SL

A

B

C

D

CLK

johnson counter
Johnson Counter

CLK

Q0

Q1

Q2

Q3

ring counter
Ring Counter

CLK

Q0

Q1

Q2

Q3

slide157

VHDL Code for a Positive-edge Triggered D Flip-flop

D flip-flop that will be used as a component.

library ieee;

use ieee.std_logic_1164.all;

entity DFlipFlop is

port( D, clock: in std_logic; Q, Qnot: inout std_logic);

end entity DFlipFlop;

slide158

VHDL Code for a Positive-edge Triggered D Flip-flop continued

architecture FlipFlopBehavior of DFlipFlop is

begin

process(D, Clock) is

begin

wait until rising_edge (clock);

if D = ‘1’ then

Q <=‘1’

else

Q <=‘0’

end if;

end process;

Qnot <= not Q;

end architecture FlipFlopBehavior;

4 bit serial in serial out shift registers using vhdl example 10 7
4-Bit Serial in/Serial out Shift Registers Using VHDL Example 10-7

library ieee;

use ieee.std_logic_1164.all;

entity SISOReg is

port( I, clock: in std_logic; Qout: buffer std_logic);

end entity SISOReg;

4 bit serial in serial out shift registers using vhdl example 10 71
4-Bit Serial in/Serial out Shift Registers Using VHDL Example 10-7

architecture ShiftRegBehavior of SISOReg is

signal Q0, Q1, Q2: std_logic;

component DFlipFlop is

port (D, Clock: in std_logic; Q, Qnot: inout std_logic);

end component DFlipFlop;

begin

FF0: DFlipFlop port map (D=>I, Clock =>clock, Q=>Q0);

FF1: DFlipFlop port map (D=>Q0, Clock=>clock, Q=>Q1);

FF2: DFlipFlop port map (D=>Q1, Clock=>clock, Q=>Q2);

FF3: DFlipFlop port map (D=>Q2, Clock=>clock, Q=>Qout);

end architecture ShiftRegBehavior;

4 bit serial in parallel out shift registers using vhdl example 10 8
4-Bit Serial in/Parallel out Shift Registers Using VHDL Example 10-8

library ieee;

use ieee.std_logic_1164.all;

entity SIPOReg is

port( I, clock: in std_logic; Q0, Q1, Q2, Q3: buffer std_logic);

end entity SIPOReg;

Defined as an output.

4 bit serial in parallel out shift registers using vhdl example 10 81
4-Bit Serial in/Parallel out Shift Registers Using VHDL Example 10-8

architecture ShiftRegBehavior of SIPOReg is

signal Q0, Q1, Q2: std_logic;

component DFlipFlop is

port (D, Clock: in std_logic; Q, Qnot: inout std_logic);

end component DFlipFlop;

begin

FF0: DFlipFlop port map (D=>I, Clock =>clock, Q=>Q0);

FF1: DFlipFlop port map (D=>Q0, Clock=>clock, Q=>Q1);

FF2: DFlipFlop port map (D=>Q1, Clock=>clock, Q=>Q2);

FF3: DFlipFlop port map (D=>Q2, Clock=>clock, Q=>Qout);

end architecture ShiftRegBehavior;

parallel in serial out shift registers
Parallel in/Serial out Shift Registers

function ShiftLoad (A, B, C,: in std_logic) return std_logic is

begin

return ((A and B) or (not B and C));

end function ShiftLoad;

parallel in serial out shift registers example 10 9
Parallel in/Serial out Shift RegistersExample 10-9

library ieee;

use ieee.std_logic_1164.all;

entity PISOReg is

port( SL,D0,D1,D2,D3, clock: in std_logic; Qout: buffer std_logic);

end entity PISOReg;

parallel in serial out shift registers example 10 91
Parallel in/Serial out Shift RegistersExample 10-9

architecture ShiftRegBehavior of PISOReg is

function ShiftLoad (A, B, C: in std_logic ) return std_logic is

begin

return (( A and B ) or ( not B and C ));

end function ShiftLoad;

signal S1, S2, S3, Q0, Q1, Q2: std_logic;

component DFlipFlop is

port (D, Clock: in std_logic; Q, Qnot: inout std_logic);

end component DFlipFlop;

begin

SL1: S1 <= ShiftLoad (Q0, SL, D1);

SL2: S2 <= ShiftLoad (Q1, SL, D2);

SL3: S3 <= ShiftLoad (Q2, SL, D3);

FF0: DFlipFlop port map (D=>D0, Clock =>clock, Q=>Q0);

FF1: DFlipFlop port map (D=>S1, Clock=>clock, Q=>Q1);

FF2: DFlipFlop port map (D=>S2, Clock=>clock, Q=>Q2);

FF3: DFlipFlop port map (D=>S3, Clock=>clock, Q=>Qout);

end architecture ShiftRegBehavior;

bidirectional shift registers in vhdl
Bidirectional Shift Registers in VHDL

library ieee;

use ieee.std_logic_1164.all;

entity BidirectionalCtr

port(RL, I, clock: in std_logic; Q0, Q1, Q2, Q3: buffer std_logic);

end entity BidirectionalCtr;

bidirectional shift registers in vhdl1
Bidirectional Shift Registers in VHDL

architecture ShiftRegBehavior of Bidirectional is

function RightLeft(A, B, C:in std_logic) return std_logic is

begin

return ((A and B) or (not B and C));

end function RightLeft;

signal S0, S1, S2, S3: std_logic;

component DFlipFlop is

port( D, Clock: in std_logic; Q, Qnot: inout std_logic);

end component DFlipFlop;

bidirectional shift registers in vhdl2
Bidirectional Shift Registers in VHDL

begin

SL0: S0 <= RightLeft(I, RL, Q1);

SL1: S1 <= RightLeft(Q0, RL, Q2);

SL2: S2 <= RightLeft(Q1, RL, Q3);

SL3: S3 <= RightLeft(Q2, RL, I);

FF0: DFlipFlop port map (D=>S0, Clock=>clock, Q=>Q0);

FF1: DFlipFlop port map (D=>S1, Clock=>clock, Q=>Q1);

FF2: DFlipFlop port map (D=>S2, Clock=>clock, Q=>Q2);

FF3: DFlipFlop port map (D=>S3, Clock=>clock, Q=>Q3);

end architecture ShiftRegBehavior;