A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits

1. A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits • Hao Yu, Yiyu Shi, Lei He Electrical Engineering Dept. UCLA • David Smart Analog Devices Inc. Partially supported by NSF, SRC and UC-MICRO fund

2. Challenge to Model Inductance current return C4 package Power Plane skin depth c4 bump Power IO current on die Power grid signal lines Cell parasitic capacitance and well capacitance Load current source that models switching gates • Loop inductance? • Where is the return path? Current return paths are not known as a priori • How to stamp a loop inductance together with other devices in the same loop to the circuit matrix? • Partial inductance by PEEC [Rueli:TMTT’74] is one choice for inductive interconnect

3. PEEC Model for Interconnect • No need to determine return path • But did we really solve the problem? • Partial inductance is associated with every piece of branch current • Mutual couplings are everywhere • L matrix is dense and not diagonal dominant • A fast simulator needs a sparse stamping of devices • Sparsifying L by truncation leads to the loss of stability • Stamping inverse inductance (L-1) element is an alternative solution • L-1 is similar to the diagonal dominant capacitance (C) [Devgan:ICCAD’02], and hence it is easy to sparsify • How to stamp it correctly in circuit matrix? How to further reduce it by model order reduction?

4. Second-order stamping and reduction by nodal analysis (NA) • NA-stamping [Sheehan:DAC99, Zheng et.al :ICCAD’02, Su et. al:ICCAD’04] has singularity at dc, and is not robust to be stamped back for time domain simulation • All above methods did not consider the structure (sparsity and hierarchy), and hence are not efficient for large-scale problem • Primary contributions of our work: • Vector potential nodal analysis (VNA) represents L-1 in a non-singular and passive stamping • Bordered-block-diagonal structured reduction (BVOR) preserves not only passivity but also sparsity and hierarchy Inverse Inductance Element Simulation • First-order stamping and reduction by modified nodal analysis (MNA) • Directly stamping leads to a non-passive model [Zheng et.al.:ICCAD’02] • Double inversion based stamping [Chen,et.al.: ICCAD’03] needs an extra cost to invert L matrix

5. Outline • Background of Circuit Stamping • VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model • BVOR Method using BBD (Bordered-block-diagonal) Representation • Experimental Results • Conclusions

6. vn+ • A network is described by two state variables: nodal voltage and branch current R Ib Vn- • The stamping is not symmetric but passive • Check (and full rank) • The stamping is non-singular • State equation is still definite at dc • L is shorted and C is open at dc • State matrix is not rank-deficient • especially for because it needs to be factorized many times Modified Nodal Analysis

7. MNA is not passive • Check • NA stamping is symmetric, seems to be passive, but is singular • Only uses nodal voltages, and it results in a susceptance S for L-1 • State equation is indefinite at dc • Both G and S become rank-deficient in NA stamping Stamping of L-Inverse in Circuit Matrix

8. NA v1 v2 v3 i1 (1/Rg+1/R) (-1/R) (0) (0) (-1/R) (1/R) (0) 1 (0) (0) (0) -1 (0) (-1) (1) sL v1 v2 v3 i1 R L Rg How to Easily Have a Singular Stamping • Why do we need branch current variable for inductance? • The inductor is shorted at dc • v2 and v3 are not independent anymore  Need a new constraint by adding a new row for i1

9. Outline • Background of Circuit Stamping • VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model • BVOR Method using BBD (Bordered-block-diagonal) Representation • Experimental Results • Conclusions

10. Define branch vector potential (flux) from a volume-integral of above differential equation [Pacelli:ICCAD’02] Vector Potential Equivalent Circuit • Differential Maxell equation • VPEC circuit equation describes L-1 elements using branch variables (ii, vi) • This leads to the proof that L-1 matrix is diagonal dominant[Yu-He:TCAD’05]

11. VNA Stamping • Using both branch and nodal variables, VPEC circuit equation leads to a new circuit stamping for L-1 • The resulting VNA state matrix is non-singular and passive

12. MNA v 1 v 2 v 3 v 4 4 v v 5 5 v v 6 6 i 1 i 2 v v 1 1 v v 2 2 v v 3 3 v v 4 4 v v 5 5 v v 6 6 i 1 i 2 p p 1 1 p p 2 2 v v 1 1 - g v v 1 1 c c x x - - c c x x v v 1 1 1 1 g + gd - g g v v 2 2 1 v v 2 2 v v 2 2 v v 3 3 - 1 v v 3 3 v v 3 3 c c v v 4 4 - - g g v v 4 4 - - c c x x c c x x v v 4 4 1 g gd + - g v v 5 5 g 1 v v 5 5 v v 5 5 v v 6 6 v v 6 6 - 1 v v 6 6 c c - 1 1 i 1 i 1 l m a 1 i 2 - 1 1 i 2 m l a 2 ( c ) ( b ) ) ( a NA VNA v v 1 1 v v 2 2 v v 3 3 v v 4 4 v v 5 5 v v 6 6 v1 v1 v2 v2 v3 v3 v4 v4 v5 v5 v6 v6 v v 1 1 - - g g v1 v1 g + g d v v 2 2 - - g g v2 v2 s s - - s s sx sx - - sx sx g v v 3 3 v3 v3 - - s s s s - - sx sx sx sx v v 4 4 - g v4 v4 g + g d - g g v v 5 5 v5 v5 sx sx - - sx sx s s - - s s v v 6 6 v6 v6 - - sx sx sx sx - - s s s s ( a ) ( b ) p 1 p 2 v1 v1 v2 v2 v3 v3 v4 v4 v5 v5 v6 v6 v v 1 1 1 1 v1 v1 cx cx - - cx cx v v 2 2 v2 v2 v3 v3 c c v v 3 3 v v 4 4 v4 v4 - - cx cx cx cx 1 v5 v5 v v 5 5 v v 6 6 v6 v6 c c ( c ) ( d ) A Circuit Example

13. qxN qxq NxN VNA Reduction (VOR) • The simple first-order model order reduction such as PRIMA [Odabasioglu,et.al:TCAD’98] can be applied • Find a small dimensioned and orthnormalized matrix V to reduce the original system size by projection • If V contains the subspace of moments, the reduced system can match the original system

14. The reduced model by VNA can be robustly stamped together with active device for time-domain simulation • SAPOR is not robust to be stamped back with active devices Advantages of VNA Reduction • The reduced model is passive • Sufficient conditions for passivity: • The VNA reduction can be performed at dc (s0=0), and hence the path tracing algorithm [Odabasioglu,et.al:TCAD’98] can be used for efficient reduction

15. Outline • Background of Circuit Stamping • VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model • BVOR Method using BBD (Bordered-block-diagonal) Representation • Experimental Results • Conclusions

16. Two-level decomposition of VNA circuit by branch-tearing • It results in decomposed blocks Yi and a global block Z0, and they are interconnected by incident matrix Xi0 • The torn branch can be a resistor, a capacitor, or an inductor • A hmetis partition is applied with specified ports for each block Two Level Decomposition by Branch Tearing • A flat presentation of VNA does not show hierarchy and hence leads to a globalized reduction and simulation • It is not efficient for large-scale circuit with inductance • Path-tracing [Odabasioglu,et.al:TCAD’98] is only effective for tree-links but not for general network

17. The BBD stamping is passive BBD Representation • The resulting system is in fact a bordered-block-diagonal (BBD) state matrices • Each block Yi is described by a set of VNA variables (vn, Al) • The global block Z0 is described by a set of torn branch variables (ib)

18. Block-diagonal structured projection [Yu-He-Tan:BMAS’05] preserves BBD structure during reduction BVOR: Localized Reduction • BBD representation enables a localized model order reduction • Each block Yi (Gi, Ci, Bi) can be reduced locally • The last block is purely composed by coupling branches, which is projected by an identity matrix • Reduced model is not only passive but also sparse, and it can be analyzed hierarchically

19. Outline • Background of Circuit Stamping • VNA Stamping using VPEC (Vector Potential Equivalent Circuit) model • BVOR Method using BBD (Bordered-block-diagonal) Representation • Experimental Results • Conclusions

20. Waveform Comparison (1) • Frequency/time domain waveform comparison of full-MNA, SAPOR [Su et.al:ICCAD’04] and VNA reduction (VOR) • The reduced models are expanded close to dc (s0 = 10Hz) with order 80 • VOR and original are visually identical in both time/frequency domain • SAPOR has larger frequency-domain error and can not converge in time-domain simulation

21. Waveform Comparison (2) • Frequency domain waveform in both low and high frequency range • The reduced models are expanded at s0 = 1GHz with order 80 • VOR is identical to the original in both ranges, • But SAPOR has large error in low-frequency range.

22. BBD Structure Preserving • BBD (two-level decomposition) representation and reduction of G and C matrices • The reduced model has preserved sparsity and BBD structure

23. Runtime Scalability Study of BVOR • Compared to SAPOR, BVOR (BBD reduction) is 23X faster to build, 30X faster to simulate, and has 51X smaller error • Compared to VOR, BVOR is 12X faster to build, 30X faster to simulate

24. Conclusions and Future Work • Propose a new circuit stamping (VNA) for L-inverse element, which is passive and non-singular • Apply a bordered-block-diagonal (BBD) structured reduction, which enables a localized model order reduction for large scale RCL-1 circuits • We are planning to extend the structured reduction to handle nonlinear system