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CSE 378 Computer Hardware Design Prof. Richard E. Haskell Email: haskell@oakland.edu Tel: 248-370-2861 Web site: www.cse.secs.oakland.edu/haskell Follow VHDL -> CSE 378 link Office Hours: Tues. and Thurs., 4:00 - 5:15 p.m. 115 Dodge Hall CSE 378 Computer Hardware Design

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CSE 378 Computer Hardware Design


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cse 378 computer hardware design
CSE 378Computer Hardware Design
  • Prof. Richard E. Haskell
    • Email: haskell@oakland.edu
    • Tel: 248-370-2861
    • Web site: www.cse.secs.oakland.edu/haskell
      • Follow VHDL -> CSE 378 link
  • Office Hours:
    • Tues. and Thurs., 4:00 - 5:15 p.m.
    • 115 Dodge Hall
cse 378 computer hardware design2
CSE 378 Computer Hardware Design
  • Lecture: 5:30 - 7:17 p.m., Tues., Thurs.
    • Room: 202 Dodge Hall
  • Lab: Tues. 12:00 - 3:00 p.m., or Tues. 7:30 - 10:30 p.m., or Thurs. 7:30 - 10:30 p.m.
    • Room: 133 SEB
course goals
Course Goals
  • Learn to design digital systems using VHDL
  • Learn to synthesize VHDL designs to Xilinx Spartan 3 series FPGAs
  • Learn to use VHDL design tools:
    • Xilinx ISE 6.2i
    • Aldec Active-HDL Simulator
  • Learn to design a small microcontroller
course objectives
Course Objectives
  • Design combinational circuits using VHDL
  • Design sequential circuits using VHDL
  • Synthesize VHDL designs to Xilinx FPGAs
  • Simulate VHDL designs using Aldec Active-HDL
  • Design a stack-based microcontroller using VHDL and synthesize it to a Xilinx FPGA
list of topics
List of Topics
  • Digital Logic Basics
  • Combinational Logic Circuits & Design
  • Sequential Circuits
  • Registers and Counters
  • RAMs and ROMs
  • Xilinx FPGAs
  • Register Transfers and Datapaths
  • Sequencing and Control
  • Design of a stack-based microprocessor
text and materials
Text and Materials
  • No required text: Class handouts and all PowerPoint lectures will be provided
  • Required: Spartan-3 board available from www.digilentinc.com
  • Enter OU378 in the Value code field
  • Required: A USB portable storage device with capacity of 64 MB or more.
references
References
  • Logic and Computer Design Fundamentals, 3rd Ed., by M. Morris Mano and Charles R. Kime, Prentice Hall, 2004.
  • The Student's Guide to VHDL, by Peter J. Ashenden, Morgan Kaufmann Publishers, Inc., San Francisco, 1998.
  • Embedded System Design: A Unified Hardware/Software Introduction, by Frank Vahid and Tony Givargis, Wiley, 2002.
  • An Introduction to Modern Digital Design, by Richard E. Haskell and Darrin M. Hanna, Oakland University, (CSE 171 text).
references cont
References (cont.)
  • Haskell, R. E. and D. M. Hanna, “A VHDL Forth Core for FPGAs,” Microprocessors and Microsystems, Vol. 28/3 pp. 115-125, Apr 2004. (available of class website).
  • VHDL Tutorial: Learn by Example http://www.cs.ucr.edu/content/esd/labs/tutorial/
  • VHDL Tutorial http://www.aldec.com/Downloads/
  • Xilinx Spartan-3 FPGA Family: Data Sheet (available on class website)
  • S3 Board Reference Manual http://www.digilentinc.com/Materials/BoardProducts.html
references cont9
References (cont.)
  • The FPGA Journal: www.fpgajournal.com
  • Additional free information about the EDA industry can be found at:www.edaboard.comwww.eg3.comwww.chipdesignmag.comwww.edacafe.comwww.eetimes.com
  • www.google.com
slide10
Labs
  • Eight weekly labs
    • Results must be demonstrated to the lab instructor by the due date for full credit
    • VHDL listing and simulation results must be signed by and turned into the lab instructor
projects
Projects
  • Groups of three or four will design and implement a digital system based on the microprocessor core designed in the class
  • The project will be demonstrated to the class during the normal final exam time
  • Results will be described in a written project report, a poster, and an oral PowerPoint presentation to the class
course web site
Course Web Site
  • Course materials can be downloaded from the following course website
    • www.cse.secs.oakland.edu/haskell/
    • follow the VHDL -> CSE 378 link
grading based on
Grading based on
  • Labs -- 25%
  • Homework -- 10%
  • 2 Exams -- 20% each
  • VHDL project
    • Project design -- 10%
    • Written report -- 10%
    • Oral Presentation -- 5%