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Predictable Scheduling for a Soft Modem. Michael B. Jones – Microsoft Research Stefan Saroiu – University of Washington. Consumer Real-Time. General-purpose Operating Systems, such as Windows 2000: maximize aggregate throughput approximate fair sharing of the resources

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Predictable scheduling for a soft modem

Predictable Scheduling for a Soft Modem

Michael B. Jones – Microsoft Research

Stefan Saroiu – University of Washington

Consumer real time
Consumer Real-Time

  • General-purpose Operating Systems,such as Windows 2000:

    • maximize aggregate throughput

    • approximate fair sharing of the resources

  • Increasing use of time-dependent tasks

    • signal processing, audio, video

  • Need support for:

    • predictable scheduling for independently developed applications

    • low latency responses

    • explicit resource allocation mechanisms

Why study soft modems
Why Study Soft Modems ?

  • Signal Processing done on host CPU:

    • requires predictable scheduling

    • requires low latency responses

  • While coexisting with other system activities

    • Soft Modem is a background real-time task

  • Successful in home computer market:

    • Low cost

    • Easy to update – software upgrade


  • Instrumented Windows 2000 performance kernel:

    • Logs predefined and custom events

    • Writes them to a memory buffer

    • Dumps buffers to disk at end of trace

  • Driver Software:

    • No source for signal processing code

  • Measurement Environment:

    • All experiments run with normal-priority spinning competitor thread

  • System:

    • Windows 2000 Professional

    • Pentium II 450 MHz (uniprocessor)

    • 384 MB ECC SDRAM - 100 MB allocated to logging

Vendor driver signal processing in interrupt int
Vendor Driver - Signal Processing in Interrupt (INT)

  • Operation of the modem:

    • 1. DMA transfers between A/D and D/A and physical memory

    • 2. When enough data samples, the modem raises an interrupt

    • 3. Inside ISR, process incoming data and provide outgoing samples, before buffers exhausted

  • Uses input and output data buffers holding 512 16-bit samples (1024 bytes/buffer)

Three additional versions
Three Additional Versions

  • DPC Version (DPC)

    • The ISR queues a DPC

    • DPC performs signal processing

  • Thread Version (THR)

    • The ISR queues a DPC that signals a thread via a semaphore

    • Thread performs signal processing

    • Experimented with several different priorities

  • Rialto/NT Version (RES)

    • Same as THR, but thread scheduled using Rialto/NT real-time periodic CPU Reservation

Interrupt rate
Interrupt Rate

3 different phases, interrupts very regular

Falls within PC 99 recommended interrupt rates of 3-16ms

Elapsed times in isr int
Elapsed Times in ISR (INT)

1.8 ms with repeatable worst case of 3.3 ms

PC 99 recommends maximum time during which a driver-based modem disables interrupts should not exceed 100 µs

Cpu utilization
CPU Utilization

14.7% sustained load on 450MHz Pentium II

Elapsed times in isr dpc
Elapsed Times in ISR (DPC)

ISR times now small, typically < 6µs

Elapsed times in queued dpc
Elapsed Times in Queued DPC

But now long DPC times: 1.8ms avg., 3.3 max (same as elapsed times in ISR for INT)

PC 99 recommends that the total execution time required for all queued DPCs should not exceed 500 µs

Samples pending to be processed int thr 24
Samples Pending to be Processed(INT & THR 24)

Small relative to 512 sample buffer size

Samples pending to be processed thr 8
Samples Pending to be Processed (THR 8)

Unsurprisingly, contention kills modem

Latency results
Latency Results

  • Set the multimedia timers to fire once every millisecond

  • Register a routine to be called every millisecond

  • Routine does very little work

    • Stores cycle counter value and sleeps again

  • Histograms show differences between recorded times and ideal times

Coexisting thread latencies int
Coexisting Thread Latencies (INT)

Maximum 5313µs between wakeups

Coexisting thread latencies dpc
Coexisting Thread Latencies (DPC)

Maximum 4396µs between wakeups

Coexisting thread latencies thr 24
Coexisting Thread Latencies (THR 24)

Maximum 2239µs between wakeups

What have we learned so far
What Have We Learned So Far?

  • Signal processing in the context of the interrupt handler is:

    • unnecessary

    • detrimental to the latencies and predictability of coexisting activities

  • Vendor choice understandable

    • For any priority there is a potentially unbounded delay between the interrupt and the thread running

  • In practice

    • Delays are reasonable for well-configured systems [Intel OSDI ’99]

    • Using interrupts extreme form of priority inflation

Two possible solutions
Two Possible Solutions

  • Rate Monotonic Analysis – determine the “right” priority assignments among all threads. Two problems:

    • Assumes cooperative priority assignment among all threads - unrealistic

    • Working priority assignment dependent upon timing requirements of all threads

      • Changes in application mix may require changes in priority assignments

  • Use a time-based real-time scheduler

    • Such as Rialto/NT

Rialto nt abstractions
Rialto/NT Abstractions

  • Two real-time software abstractions:

    • CPU Reservations – ongoing reservation for at least X time units out of every Y units for a thread

    • Time Constraints – one-shot time reservation for specified amount of work between start time and deadline

  • The Soft Modem work only uses CPU Reservations

Rialto nt implementation
Rialto/NT Implementation

  • Rialto/NT developed on top of Windows 2000 priority scheduler

  • Limitations:

    • CPU Reservations must be integer multiples of milliseconds

    • Frequency of reservations must be power-of-two multiple of 1ms

Samples pending to be processed res 2ms 8ms 25
Samples Pending to be Processed (RES 2ms/8ms – 25%)

Fits well within 512-sample buffer size

Coexisting thread latencies res 2ms 8ms 25
Coexisting Thread Latencies (RES 2ms/8ms – 25%)

Maximum 1971µs between wakeups

File transfer times
File Transfer Times

Results for 10 copies of 200,000 bytes each

For 1/8, 2/15, 3/17, 4/17, 7/20 no test passed

Modem reservation ranges
Modem Reservation Ranges

Sensitivity to both percentage and gaps

If period < 12.5ms, must get 14.7% to work

If period > 12.5ms, (period – amount) >= 12.5ms must also hold


  • Signal Processing in interrupt context is:

    • Unnecessary

    • Detrimental to the predictability and latencies of the coexisting activities

  • The DPC version has similar problems

  • Threads help alleviate these problems

    • Modem runs well with real-time priorities and non-real-time competition

    • However modem threads may interfere with other threads

  • Real-time scheduler allows

    • Control over modem’s degree of interference with other time-sensitive activities

    • Performance isolation for threads using reservations

Industry perspective
Industry Perspective

  • Vendor did build their own THR version

    • Worked fine during normal load

    • However, modem was starved when

      • copying data between two IDE devices

      • using USB scanner (Intel 440BX chipset) that turned off interrupts for 30-50 ms

    • Therefore they shipped the INT version

  • Vendor is willing to be a “good citizen”

    • if ensured that others would be as well

  • Systematic latency timing verification of components is needed to enforce good behavior

Soft dsl is coming
Soft DSL is Coming

  • More demanding than soft modems

    • 4ms processing period

  • G.lite

    • 1.531Mbps downstream and 512Kbps upstream

    • ~ 25% of a 600 MHz Pentium III

  • Full rate DSL

    • 3.062Mbps downstream and 512Kbps upstream

    • Nearly 50% of a 600 MHz Pentium III

  • Soft Bluetooth period 312.5µs

Further research possibilities
Further Research Possibilities

  • Soft DSL studies

  • Multiple soft devices within the same machine

  • Similar studies on multiprocessors

For more information
For More Information

  • See the authors:

    • Mike Jones



    • Stefan Saroiu



  • See related papers at Mike’s web site