ERD Architecture Benchmarking: The NRI MIND Activity. Ralph K. Cavin, III, Kerry Bernstein & Jeff Welser July 12, 2009 San Francisco, CA. Goals of the NRI/MIND Benchmarking Project. Develop circuit/subsystem level examples of the applications of novel devices
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Ralph K. Cavin, III, Kerry Bernstein &
July 12, 2009
San Francisco, CA
Architectural Innovations haven’t been the major driver for system performance
Analysis of high perfarchitectures and the technologies they were built in, examining devicevs arch contributions to throughput
- Predominant influence on SPEC2000 is from device technology - Modest contributions from architecture
New Switch Ideas
Encrypt / Decrypt
Compr / Decompr
Reg. Expression Scan
Discrete COS Trnsfrm
Bit Serial Operations
H.264 Std Filtering
DSP, A/D, D/A
Example: Cryptography Hardware Acceleration
Operations required: Rotate, Byte Alignmt, EXORs, Multiply, Table Lookup
Circuits used in Accel: Transmission Gates (“T-Gates”)
New Switch Opportunity: A number of new switches (i.e. T-FETs) don’t have (example) thermionic barriers: won’t suffer from CMOS Pass-gate VT drop, Body Effect, or Source-Follower delay.
Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.
Gary Bernstein1, X. Sharon Hu2, Michael Niemier2, Wolfgang Porod1
M. Tanvir Alam1, Michael Crocker2, Aaron Dingler2,
Steve Kurtz2, Shawn Liu2, M. Jafar Siddiq1, Edit Varga1
1Department of Electrical Engineering, 2Department of Computer Science and Engineering
Base performance projections on adder design.
Because of sensitivity to sub-threshold slope, threshold voltage … energy, delay can vary significantly from technology to technology.
These are best data points for CMOS
(0.3V - 1V)
V & mr
With mr = 1, can still see ~15X performance gain due to higher throughput
If higher supply voltage to match delay, ~7X energy savings
With mr = 5, ~17x (NP) and ~158X (P) energy savings with better performance