erd architecture benchmarking the nri mind activity n.
Skip this Video
Download Presentation
ERD Architecture Benchmarking: The NRI MIND Activity

Loading in 2 Seconds...

play fullscreen
1 / 15

ERD Architecture Benchmarking: The NRI MIND Activity - PowerPoint PPT Presentation

  • Uploaded on

ERD Architecture Benchmarking: The NRI MIND Activity. Ralph K. Cavin, III, Kerry Bernstein & Jeff Welser July 12, 2009 San Francisco, CA. Goals of the NRI/MIND Benchmarking Project. Develop circuit/subsystem level examples of the applications of novel devices

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
Download Presentation

PowerPoint Slideshow about 'ERD Architecture Benchmarking: The NRI MIND Activity' - irina

Download Now An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
erd architecture benchmarking the nri mind activity

ERD Architecture Benchmarking:The NRI MIND Activity

Ralph K. Cavin, III, Kerry Bernstein &

Jeff Welser

July 12, 2009

San Francisco, CA

goals of the nri mind benchmarking project
Goals of the NRI/MIND Benchmarking Project
  • Develop circuit/subsystem level examples of the applications of novel devices
  • Evaluate the circuits/subsystems in the energy-time-space context versus CMOS implementations
  • Determine most promising applications for emerging devices with an emphasis on integration with CMOS

Architectural Innovations haven’t been the major driver for system performance

Analysis of high perfarchitectures and the technologies they were built in, examining devicevs arch contributions to throughput

- Predominant influence on SPEC2000 is from device technology - Modest contributions from architecture

four architectural projections
Four Architectural Projections
  • CMOS is not going away anytime soon. Charge (state variable), and the MOSFET (fundamental switch) will remain the preferred HPC solution until new switches appear as the long term replacement solution in 10-20 years.
  • Hdwre Accelerators execute selected functions faster than software performing it on the CPU.Accelerators are responsible for substantial improvements in thru-put.
  • Alternative switches often exhibit emergent, idiosyncratic behavior. We should exploit them.Certain physical behaviors may emulate selected HPC instruction sequences. Some operations may be superior to digital solutions.
  • New switches may improve high-utilitization acceleratorsThe shorter term supplemental solution (5-15 years) improves or replaces accelerators “built in CMOS and designed for CMOS”, either on-chip or on-3D-stack or on-planar

Matching Logic Functions & New Switch Behaviors

New Switch Ideas

Popular Accelerators

Single Spin

Spin Domain








Encrypt / Decrypt

Compr / Decompr

Reg. Expression Scan

Discrete COS Trnsfrm

Bit Serial Operations

H.264 Std Filtering


Viterbi Algorithms

Image, Graphics


Example: Cryptography Hardware Acceleration

Operations required: Rotate, Byte Alignmt, EXORs, Multiply, Table Lookup

Circuits used in Accel: Transmission Gates (“T-Gates”)

New Switch Opportunity: A number of new switches (i.e. T-FETs) don’t have (example) thermionic barriers: won’t suffer from CMOS Pass-gate VT drop, Body Effect, or Source-Follower delay.

Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.

examples of benchmarking work in progress
Examples of Benchmarking Work in Progress
  • Magnetic Tunnel Junction one-bit adder
  • Magnetic Logic for one-bit adder
  • Magnetic Ring Logic Devices
  • Many other devices are being evaluated in a variety of circuit configurations.
background mtj
Background - MTJ
  • Researchers have been investigating post-CMOS devices for many years. In short term, people are looking for switches that supplement CMOS and are CMOS-compatible, supporting ultra-low power operation.
  • MTJ (Magnetic Tunnel Junction) is one of the strongest candidate which is available in practice rather than only in theory.
    • Excellent for memory and storage.
      • STT-RAM using MTJ is strong candidate for universal memory.
    • For logic design, good or not?
      • Any memory device can also be used to build logic circuits, in theory at least, and MTJ is no exception.
      • The discovery of spin torque transfer (STT) makes MTJ scalable and completely CMOS-compatible.
mtj based dycml 1 bit full adder
MTJ-based DyCML 1 Bit Full Adder
  • MTJ is used as both a memory cell and functional input.
  • The switching of MTJ conducted by STT using control signals WL, BL.
  • It is actually a CMOS-MTJ-combined version of DyCML. Thus, it is more reasonable to compare it with CMOS-based DyCML to see MTJ’s impact.
  • ED Curve of 65nm process




nanomagnet logic nml
Nanomagnet Logic (NML)


Gary Bernstein1, X. Sharon Hu2, Michael Niemier2, Wolfgang Porod1


M. Tanvir Alam1, Michael Crocker2, Aaron Dingler2,

Steve Kurtz2, Shawn Liu2, M. Jafar Siddiq1, Edit Varga1


1Department of Electrical Engineering, 2Department of Computer Science and Engineering

comparison to cmos
Comparison to CMOS
  • Hard to compare magnet to transistor
    • Need to make technology comparison at functional unit level; consider initial projections here
  • Natural comparison = low power CMOS systems, sub-threshold, etc.







Base performance projections on adder design.




Because of sensitivity to sub-threshold slope, threshold voltage … energy, delay can vary significantly from technology to technology.

These are best data points for CMOS

(0.3V - 1V)

V & mr


(pJ ns)

With mr = 1, can still see ~15X performance gain due to higher throughput

If higher supply voltage to match delay, ~7X energy savings

With mr = 5, ~17x (NP) and ~158X (P) energy savings with better performance

magnetic ring logic devices benchmarks metrics
Magnetic Ring Logic Devices – Benchmarks/Metrics
  • Caroline Ross - MIT
  • These devices work by the movement of domain walls around thin film rings with general structure Hard layer/Spacer/Soft layer, e.g. Co/Cu/NiFe or Co/MgO/NiFe.
  • Rings can have several remanent states with different resistances. This is useful for multibit memory. However, digital logic uses two levels so in these examples, some of the complexity available in ring devices is wasted
  • NAND/NOR configurations are being analyzed.
  • The Nanoelectronics Research Initiative benchmarking project should be nearing completion by mid-August, 2009
  • The ERA section plans to provide a summary of findings for 2009