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## Basic Knowledge of Data Converters

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**Agenda**• Data Converter Overview • ADC/DAC Basics • Sampling Theory • ADC Architectures • SAR • Delta-Sigma • Pipeline • Flash • DAC Architectures • R-2R • String • Data Converter Specifications/ Test (how to get them from DATASHEET) • DC Spec. • AC Spec. • ADC/DAC Nomenclature**What is ADC**Analog to Digital**What is DAC**Digital to Analog**ADC/DAC Basic**• Sampling Theory • ADC Architectures • Delta-Sigma • SAR • Pipeline • Flash • DAC Architectures • R-2R • String**Basic ADC Theory**• Analog signal is sampled • The sampled analog signal is compared to one or more reference voltages • The result of the comparison is converted by digital logic to a binary number.**SHANNON’S information theorem NYQUIST’S Criteria**• Shannon: • An analog signal with a Bandwidth of fa must be sampled at a rate fs>2fa in order to avoid the loss of information. • The Signal Bandwidth may extend from DC to fa (Baseband Sampling) or from f1 to f2, where fa = f2-f1 (Undersampling, or Super-Nyquist). • Nyquist: • If fs<2fa, then a phenomenon called aliasing will occur. • Aliasing is used to advantage in undersampling applications**Input Waveform**Sampled Output Sampling Function f(t) g(t) h(t) f(t2) Unit Pulses f(t3) f(t4) f(t1) t1 t2 t3 t4 t t t1 t2 t3 t4 t T Fourier Transform Input Spectrum Sampled Spectrum G(f) F(f) f1 f1 fs fs+f1 2fs-f1 f f Sampling Theory X = Sampling Spectrum H(f) Nyquist region = * f fs = 1/T 2fs * NYQUIST'S THEOREM: fs-f1 > f1 fs > 2 ´ f1 14-8**Why Oversample?**• TO MOVE ALIASING FREQUENCY FURTHER FROM THE DESIRED SIGNAL. • TO RELIEVE ANTIALIASING AND RECONSTRUCTION FILTER REQUIREMENTS • COST • COMPLEXITY • RESPONSE • TO ALLOW FOR LOWER APPARANT INPUT NOISE BY FILTERING IN THE DIGITAL DOMAIN. • TO ALLOW FOR LOWER APPARANT INPUT NOISE BY SPREADING THE QUANTIZING NOISE OVER A WIDER BANDWIDTH.**Sampling ADC Quantization Noise**SIGNAL OUTPUT RMS QUANTIZATION NOISE = q/ 12 f f s s 2**Analog signal fa sampled @ fs has images (aliases) at**|±Kfs ±fa|, K = 1, 2, 3, ...**Analog filter requirement for fo = 10MHz: fS = 30MSPS AND fS**= 60MSPS**Why Undersample?**• The AC bandwidth of the “analog portion” of an ADC is usually wider than the maximum sample rate. • Nyquist says that the BANDWIDTHnot the FREQUENCY of the signal must be ½ sampling rate. • You can process the spectrum at harmonics of the sample rate as well**Intermediate Frequency (IF) signal at 72.5MHz (±2MHz) is**aliased between DC and 5MHz f = 10.000 MSPS s f = 10.000 MHz 7f s = 70.000 MHz s 2f 3f 6f 7f dc f 4f 5f s s s s s s s 0 10 20 30 40 50 60 70 BASEBAND SIGNAL: ALIAS: 72.5 ± 2 MHz dc TO 5 MHz**Anti-aliasing filter for undersampling**f f - f 1 f s 1 2f - f 2 s 2 DR S IG NA LS IMAGE IMAGE O F IMAGE I NT E RE ST 0.5 f f 1.5 f 0 2f S S S S STOPBAND ATTENUATION = DR Bandpass filter specifications TRANSITION BAND: f TO 2f - f 2 s 2 CORNER FREQUENCIES: f , f 1 2 f c f TO f - f 1 s 1**Quantization Error**• Analog signals are continuous • Digital signals have discrete values • A digital word that is converted to an analog signal will always contain errors • Quantization Error or Noise is dependent on the number of bits used in the conversion**Data Converters’ Architectures**• ADCs • Delta Sigma • SAR • Pipeline • Flash • DAC • R-2R • String Customers Talk Architecture???Should you be scared - NOCan you handle it - TRYJust know the key characteristics and you have just focused in on your device selection**A/D Converter**- SAR- Pipeline- Flash- Delta Sigma**ADC Architectures:Speed, Resolution, and Latency Analogy**Delta Sigma • 16 to 24 bits of resolution • Typically Slow 10SPS to 105kSPS • Long Latency • If I was a camera I would have my aperture open longer SAR • 8 to 18 bits of resolution • ~50kSPS to 4MSPS • No latency • If I was a camera I would be have fast shutter speed Pipeline • 8 to 14 bits of resolution • Up to over 300 MSPS • Some clock cycle latency • I want to be a video camera when I grow up Flash • 8 to 10 bits of resolution • Up to over 1 GSPS • no latency • I just want to be FLASH**TI Analog to Digital Families**300 M 100 M 10 M 1 M 500 k 100 k 10 k 1 k 0 • Advantages • Higher Speeds • Higher Bandwidth • Disadvantages • Lower Resolution • Pipeline Delay/Data Latency • More power Pipeline Delta Sigma • Advantages • High Resolution • Low cost • Low Power typically • High Stability • (averages and filters out noise) • Disadvantages • High Latency • Low Speed typically SAR • Advantages • No Latency (happens immediately) • High Resolution and Accuracy (<=18-bits) • Typically Low Power • Easy to Use and Multiplex • Disadvantages • Typically sample Rates Limited to • Approximately 4 MHz Speed: Sample Rate in SPS Delta Sigma 6 8 10 12 14 16 18 20 24 Accuracy (Resolution in bit)**An “n” bit SAR converter takes n cycles to complete a**conversion. From most to least significant bit (MSB to LSB) simple compare functions are done and, when a bit is a 1, that amount of voltage is subtracted from the input signal. SAR’s are workhorse converters… easy to use… simple to understand… but are limited in both resolution and speed. TI has MANY SAR ADCs. ADC – Successive Approximation Register (SAR) Architecture FS: Full Scale VIN S/H + - FS fS SAR and Control Logic Clock FS 2 MSB Data Out LSB 0 D/A Converter Ref MSB LSB**ADC – Pipeline Architecture**Pipeline converters are another high speed architecture. Several lower resolution converters are put together to result in a fast conversion time. Generally lower power and lower cost than Flash converters, the main disadvantage of a Pipeline converter is that it takes as many clock cycles as there are stages to output the data resulting in latency. STAGE 1 STAGE N Sample Hold Amplifier Sample Hold Amplifier ANALOG INPUT + + ADC S S - - SAMPLE HOLD AMPLIFIER ADC ADC DAC DAC REGISTER REGISTER TI has many Pipeline converters! PARALLEL DIGITAL OUTPUT**Latency SARs have none….OK, just a little**ADS7881 12 bits 4MSPS Snapshot Acquisition Time Conversion Time = 150ηs Aperture delay = 2ηs If it was a 12 bit pipeline with 2 bits/stage, you would need: 150 ηs Conv t Delay = 6.6MSPS X 6 clock cycle delay = 40MSPS**Pipeline A/D ConverterTiming and Data Latency**Sample Points S5 S4 S8 S1 S9 Analog Input S2 S6 S3 S7 Track Hold Clock Data Latency, 6.5 clock cycles Track Hold Internal S/H n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Output Data n-7 n-6 n-5 n-4 n-3 n-2 n-1 n**Pipeline A/D ConverterSignal Encoding: SAR vs. Pipeline**• SAR: Serial Encoding Sample #1 MSB B2 B3 B4 B5 B6 B7 LSB Conversion Time • Pipeline: Parallel Encoding Sample #1 MSB B2 B3 B4 B5 B6 B7 LSB Conversion Time Sample #2 MSB B2 B3 B4 B5 B6 B7 LSB Sample #3 MSB B2 B3 B4 B5 B6 B7 LSB**And Now for something completely different**Delta Sigma’s**Delta-Sigma Overview**• What is a delta-sigma ADC? • A 1-bit converter that uses oversampling (can be multi-bit) • “Delta” = comparison with 1-bit DAC • “Sigma” = integration of the Delta measurement • What is the advantage of delta-sigma? • Essentially digital parts which result in low cost • High resolution • What are the disadvantages? • Limited frequency response • Most effective with continuous inputs • Latency 3**S D Converters – Functional Block Diagram**1-bit wide n-bits wide PGA Analog Modulator Digital Filter Analog Input Digital Output • Advantages: • Minimum analog components • Integrates easily with digital logic • Oversampling reduces inband noise • Disadvantages: • Speed limited to upper audio range**Delta-Sigma A/D Signal Path**You are here**Delta-Sigma A/D Signal Path**TIME DOMAIN FREQUENCY DOMAIN**Delta-Sigma A/D Signal Path**TIME DOMAIN FREQUENCY DOMAIN**Delta-Sigma A/D Signal Path**TIME DOMAIN FREQUENCY DOMAIN**Delta-Sigma A/D Signal Path**TIME DOMAIN FREQUENCY DOMAIN**Delta-Sigma A/D Signal Path**TIME DOMAIN FREQUENCY DOMAIN**Delta-Sigma A/D Signal Path**OUTPUT OF DECIMATING FILTER SIGNAL FROM MODULATOR DECIMATING FILTER**Oversampling, digital filter, NOISE SHAPING, AND DECIMATION**A fs QUANTIZATION NOISE = q / 12 q = 1 LSB Nyquist Operation ADC fs 2 Oversampling + Digital Filter + Decimation fs B Kfs fs DIGITAL FILTER ADC DIGITAL FILTER DEC REMOVED NOISE fs 2 Kfs 2 Oversampling + Noise Shaping + Digital Filter + Decimation C Kfs fs REMOVED NOISE SD MOD DIGITAL FILTER DEC fs 2 Kfs Kfs 2 Kfs**The Delta-Sigma Modulator**+ + - - Sigma Delta Signal input, X1 X3 To Digital Filter X2 X4 Difference Amp Integrator Comparator (1-bit ADC) VMax X5 1-bit DAC 4**Averaging Filters**0V Full-scale Delta-Sigma Modulator 1-bit data DC input levels 1-bit data streams 1/2 full-scale input 1/4 full-scale input 3/4 full-scale input 1 1 1 0 Average 0 Average 1 Average 1 = 0.5 0 = 0.25 1 = 0.75 0 0 0 1 1 1 0 0 1 1 0 1 0 0 0