COMP541 More on State Machines; and Video Monitors

1. COMP541More on State Machines;and Video Monitors Montek Singh Feb 22, 2012

2. Outline • Last Friday’s lab • Tips/discussion • How to generate video signal

3. What did you have trouble with in lab?

4. How about making a BCD stop watch? • Each digit counts 0 to 9, and then wraps around • i.e., display is decimal number, not hex • Do the following: • Separate the 16-bit number into four 4-bit numbers • reg [3:0] A3, A2, A1, A0; • For A0: on each clock tick… • if this digit is 9, change it to 0, else add 1 to it • For A1, A2, A3: on each clock tick… • if all lower A’s are at 9, then • if this digit is 9, change it to 0, else add 1 to it • else this digit does not change • Slow it down to tick once per second • have a separate counter to count 226 or 227 clock ticks • update the 4-digit number only whenever this counter fills up!

5. Reminder: Good Verilog Practices • Best to use single clock for all FFs • Make all signals synchronous to one clk • No: (posedge button) etc. • No: (posedge button or negedge button) • not supported by current board • just use either posedge or negedge only • Avoids “weird” and frustrating problems • Multiple modules • Tested individually • Top level has input and outputs • One module per file • Just to make it easier to follow and test

6. Reminder: Comb. vs. sequential • Continuous assignment (assign) • works only for combinational logic wire X; assign X = … • Procedural assignment (always/if-else/case-default) • works for sequential logic • generate FFs and latches (plus gates) • also for combinational but only under some strict conditions • can optimize away unnecessary registers … • … if synthesizer detects all possibilities covered (i.e. no state needed) • Look at the synthesizer log

7. Procedural Assignment 1 module C2(output reg C = 0, input A, input B); always @ (*) case ({A, B}) 2'b11: C <= 1; default: C <= 0; endcase endmodule • Schematic next page

8. Schematic • LUT is a look-up table • Double clicking it shows

9. Procedural Assignment 2 module C1(output reg C = 0, input A, input B); always @ (*) begin if(A == 1 && B == 1) C <= 1; end endmodule • Synthesizer now says WARNING:Xst:737 - Found 1-bit latch for signal <C>. WARNING:Xst:1426 - The value init of the FF/Latch C hinder the constant cleaning in the block C1.

10. Schematic • Explanations • LDE is latch • Small box is a buffer for the clock • Vcc or Vdd is voltage supply

11. In fact… • If I change the INIT of C to: output reg C = 1 • Synthesizer says INFO:Xst:1304 - Contents of register <C> in unit <C1> never changes during circuit operation. The register is replaced by logic.

12. Schematic module C1(output reg C = 1, input A, input B); always @ (A or B) begin if(A == 1 && B == 1) C <= 1; end endmodule

13. VGA Monitors

14. How Do Monitors Work? • Origin is TV, so let’s look at that • LCDs work on different principle, but all signaling still derived from TV of 1940s • Relies on your brain to do two things • Integrate over space • Integrate over time

15. Many Still Images • Video (and movies) are a series of stills • If stills go fast enough your brain interprets as moving imagery • 50-60 Hz or more to not see flicker • “1 Hz” means once per second • In fact, even if the scene does not change… • … a single “still” image is displayed repeatedly over time • Why? Phosphor persistence varies

16. Cathode Ray Tube (CRT) From wikipedia: http://en.wikipedia.org/wiki/Cathode_ray_tube

17. Deflection Coils

18. Simple Scanning TV • Electron beam scans across • Turned off when • Scanning back to the left (horizontal retrace ----) • Scanning to the top (vertical retrace ____)

19. Scanning: Interlaced vs. Progressive • TVs use interlacing • Every other scan line is swept per field • Two fields per frame (30Hz) • Way to make movement less disturbing • Computers use progressive scan • Whole frame refreshed at once • 60Hz or more, 72Hz looks better • Similar notation used for HD • i = interlaced (1080i) • p = progressive (1080p) • which better?

20. Color • Three colors of phosphor • three beams, one each for the three phosphors • Black: all beams off • White: all beams on Picture is a bit misleading. Mask (or aperture grill) ensures beams hit only correct color phosphor.

21. What about LCD? • How do LCD monitors work? • internals are very different • no beams, tubes • made up of tiny LCD cells • However, external signaling is the same! • for compatibility • Same goes for micro-mirror projectors

22. VGA Signaling • Timing signals • horizontal sync • vertical sync • Color values • R, G, B

23. VGA Timing • You supply two pulses • hsyncand vsync • allow the monitor to lock onto timing • One vsync per frame • One hsync per scan line • hsync does not stop during vsync pulse Image from dell.com

24. Horizontal Timing Terms • Horizontal timing: • hsync pulse • Back porch (left side of display) • Active Video • Video should be blanked (not sent) at other times • Front porch (right side) Picture not accurate for our case; just for illustration. Video and HSYNC not on same wire

25. Horizontal Timing 640 Horizontal Dots Horiz. Sync Polarity NEG Scanline time (A) 31.77 us Sync pulse length (B) 3.77 us Back porch (C) 1.89 us Active video (D) 25.17 us Front porch (E) 0.94 us This diagram shows video as a digital signal. It’s not – video is an analog level. us = microsecond Image from http://www.epanorama.net/documents/pc/vga_timing.html

26. Vertical Timing (note ms, not us) Vert. Sync Polarity NEG Vertical Frequency 60Hz Total frame time (O) 16.68 ms Sync length (P) 0.06 ms Back porch (Q) 1.02 ms Active video (R) 15.25 ms Front porch (S) 0.35 ms

27. Timing as Pixels • Easiest to derive all timing from single-pixel timing • How “long” is a pixel? • Active video / number of pixels • 25.17 us / 640 = 39.32ns • Conveniently close to 25 MHz – just use that • Actual VESA spec is 25.175 MHz

28. Standards • 640 x 480 (sometimes x 60Hz) is “VGA” • I will give you spec sheets in lab • You can try for 800x600 at 60 Hz (40 MHz exactly) • or 800x600 at 72 Hz (50 MHz exactly) • Note that some standards have vsync and hsync positive true, some negative true • choose correct polarity • determine by experimentation!

29. Color Depth • Voltage of each of RGB determines color • 3-bit for red and green • 2-bit for blue (why?) • All on for white

30. What To Do Friday • First finish previous lab • Make Verilog module to generate • hsync, vsync, horizontal count, vertical count, and signal to indicate active video • Use higher-level module to drive RGB using counts gated by active • Just do something simple; need to meet 25MHz constraint • Later we will use memory addressed by counts to make terminal I will post lab writeup on website by Thursday

31. What do you Need for VGA? • Think first • Need counter(s)? • Will you need a state machine? • Sketch out a design • Block diagram • Test individually in lab • Keep in mind • Verilog has all these operators (and more; see Verilog ref.) ==, <, >, <=, >=

32. Future Labs Preview • VGA timing generator (Feb 24) • Character terminal (learn memories) • MIPS datapath • Add load/store; add branching • Add peripherals (joystick or keyboard) • Final project

33. VGA Links • VGA Timing • Recommended: http://tinyvga.com/vga-timing • http://www.epanorama.net/documents/pc/vga_timing.html • Interesting • http://www.howstuffworks.com/tv.htm • http://computer.howstuffworks.com/monitor.htm • http://www.howstuffworks.com/lcd.htm • http://plc.cwru.edu/

34. Next Week • Sequential Timing • Memories • Homework #1 due (Wed, Feb 29)