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实验七 VHDL 语言层次化法时序电路编程实验. 一、实验目的. 掌握顶层 VHDL 语言设计和元件模块调用方法。. 二、实验预习要求. 了解 TOP-DOWN 层次设计方法基本设计思想。. 三、实验要求. 明设计过程,输入设计程序,下载测试验证。. 四、实验内容. 基础实验: 1. 试用 4 位 2 进制和 7 段译码模块设计 1 个显示 0-F 的程序; 提高实验: 2. 试用 26 进制加法计数和组合电路模块设计 1 个显示英文字母的程序 。. 五、实验步骤. 1.0-F 显示电路设计. (1) 4 位 2 进制加法计数器设计. ① 输入设计.

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实验七 VHDL语言层次化法时序电路编程实验

一、实验目的

掌握顶层VHDL语言设计和元件模块调用方法。

二、实验预习要求

了解TOP-DOWN层次设计方法基本设计思想。

三、实验要求

明设计过程,输入设计程序,下载测试验证。

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四、实验内容

基础实验:

1.试用4位2进制和7段译码模块设计1个显示0-F的程序;

提高实验:

2.试用26进制加法计数和组合电路模块设计1个显示英文字母的程序。

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五、实验步骤

1.0-F显示电路设计

(1)4位2进制加法计数器设计

①输入设计

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③时序仿真

④下载测试

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2.英文字母显示电路设计

(1)26进制加器计数器设计

①输入设计

②编译

③入库

(2)7段译码电路设计

①输入设计

②编译

③入库

(3)英文字母显示电路设计

①输入设计

②编译

③时序仿真

④下载测试

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六、实验报告要求

写出顶层和模块程序,总结层次化设计到最后下载测试的整个过程,画出仿真图,总结说明实验结果。

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七、参考程序

4位2进制加法计数器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT4B IS

PORT(CLK:IN STD_LOGIC;

RST:IN STD_LOGIC;

ENA:IN STD_LOGIC;

OUTY:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

COUT:OUT STD_LOGIC);

END CNT4B;

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ARCHITECTURE BEHAV OF CNT4B IS

SIGNAL CQI: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

P_REG:PROCESS(CLK,RST,ENA)

BEGIN

IF RST='1'THEN CQI<="0000";

ELSIF CLK'EVENT AND CLK='1'THEN

IF ENA='1' THEN CQI<=CQI+1;

ELSE CQI <= "0000";

END IF; END IF; OUTY<=CQI;

END PROCESS P_REG;

COUT<=CQI(0) AND CQI(1) AND CQI(2) AND CQI(3);

END BEHAV;

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7段译码电路程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DECL7S IS

PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );

END DECL7S;

ARCHITECTURE ONE OF DECL7S IS

BEGIN

PROCESS(A)

BEGIN

CASE A IS

WHEN "0000"=> LED7S <= "0111111";

WHEN "0001"=> LED7S <= "0000110";

WHEN "0010"=> LED7S <= "1011011";

WHEN "0011"=> LED7S <= "1001111";

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WHEN "0100"=> LED7S <= "1100110";

WHEN "0101"=> LED7S <= "1101101";

WHEN "0110"=> LED7S <= "1111101";

WHEN "0111"=> LED7S <= "0000111";

WHEN "1000"=> LED7S <= "1111111";

WHEN "1001"=> LED7S <= "1101111";

WHEN "1010"=> LED7S <= "1110111";

WHEN "1011"=> LED7S <= "1111100";

WHEN "1100"=> LED7S <= "0111001";

WHEN "1101"=> LED7S <= "1011110";

WHEN "1110"=> LED7S <= "1111001";

WHEN "1111"=> LED7S <= "1110001";

END CASE;

END PROCESS;

END ;

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0-F显示电路参考程序

library ieee;

use ieee.std_logic_1164.all;

ENTITY TOPF IS

PORT(CLKQ:IN Std_Logic;

OUTQ:OUT Std_Logic_VECTOR(6 DOWNTO 0));

END TOPF;

ARCHITECTURE FD1 OF TOPF IS

COMPONENT CNT4B --调用CNT4B模块

PORT(CLK:IN Std_Logic;

Q:OUT Std_Logic_VECTOR(3 DOWNTO 0));

END COMPONENT;

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COMPONENT DECL7S --调用DECL7S模块

PORT(A:IN Std_Logic_VECTOR(3 DOWNTO 0);

LED7S:OUT Std_Logic_VECTOR(6 DOWNTO 0));

END COMPONENT;

SIGNAL AA: Std_Logic_VECTOR(3 DOWNTO 0);

BEGIN

U1:CNT4B PORT MAP(CLK=>CLKQ,Q=>AA);

U2:DECL7S PORT MAP(A=>AA,LED7S=>OUTQ);

END FD1;