Arithmetic

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# Arithmetic - PowerPoint PPT Presentation

Arithmetic. Where we've been: Performance (seconds, cycles, instructions) Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: Implementing the Architecture. operation. a. ALU. 32. result. 32. b. 32. Arithmetic.

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## Arithmetic

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Presentation Transcript
1. Arithmetic • Where we've been: • Performance (seconds, cycles, instructions) • Abstractions: Instruction Set Architecture Assembly Language and Machine Language • What's up ahead: • Implementing the Architecture

2. operation a ALU 32 result 32 b 32 Arithmetic • We start with the Arithmetic and Logic Unit

3. Numbers • Bits are just bits (no inherent meaning)— conventions define relationship between bits and numbers • Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2n-1 • Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers • How do we represent negative numbers? i.e., which bit patterns will represent which numbers? • Octal and hexadecimal numbers • Floating-point numbers

4. Possible Representations of Signed Numbers • Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 • Issues: balance, number of zeros, ease of operations. • Two’s complement is best.

5. maxint minint MIPS • 32 bit signed numbers:0000 0000 0000 0000 0000 0000 0000 00002 = 0100000 0000 0000 0000 0000 0000 0000 00012 = +1100000 0000 0000 0000 0000 0000 0000 00102 = +210...0111 1111 1111 1111 1111 1111 1111 11102 = +2,147,483,646100111 1111 1111 1111 1111 1111 1111 11112 = +2,147,483,647101000 0000 0000 0000 0000 0000 0000 00002 = –2,147,483,648101000 0000 0000 0000 0000 0000 0000 00012 = –2,147,483,647101000 0000 0000 0000 0000 0000 0000 00102 = –2,147,483,64610...1111 1111 1111 1111 1111 1111 1111 11012 = –3101111 1111 1111 1111 1111 1111 1111 11102 = –2101111 1111 1111 1111 1111 1111 1111 11112 = –110

6. Two's Complement Operations • Negating a two's complement number: invert all bits and add 1 • Remember: “Negate” and “invert” are different operations. You negate a number but invert a bit. • Converting n bit numbers into numbers with more than n bits: • MIPS 16 bit immediate gets converted to 32 bits for arithmetic • copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 "sign extension" • MIPS load byte instructions lbu: no sign extension lb: sign extension

7. Addition & Subtraction • Unsigned numbers just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101 1101 0001 0001 • Two's complement operations easy • subtraction using addition of opposite number 0111 + 1010 10001 (result is 0001, carry bit is set) • Two's complement overflow (result not within number range) • e.g., adding two 4-bit numbers does not yield an 4-bit number 0111 + 0011 1010 (result is - 6, overflow bit is set)

8. Detecting Overflow • No overflow when adding a positive and a negative number • No overflow when signs are the same for subtraction • Overflow occurs when the value affects the sign: • overflow when adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive and get a negative • or, subtract a positive from a negative and get a positive • Consider the operations A + B, and A – B • Can overflow occur if B is 0 ? No. • Can overflow occur if A is 0 ? Yes.

9. Effects of Overflow • An exception (interrupt) occurs • Control jumps to predefined address for exception • Interrupted address is saved for possible resumption • Details based on software system / language • example: flight control vs. homework assignment • Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons

10. Logical Operations • and, andi: bit-by-bit AND • or, ori: bit-by-bit OR • sll: shift left logical • slr: shift right logical • 0101 1010 shifting left two steps gives 0110 1000 • 0110 1010 shifting right three bits gives 0000 1011

11. operation op a b res 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 result Logical unit • Let's build a logical unit to support the and and or instructions • we'll just build a 1 bit unit, and use 32 of them • op=0: and; op=1: or • Possible Implementation (sum-of-products): result = a • b + a • op + b • op a b

12. S MUX EN A C B 0 0 _ G 3 1 0 1 2 Operation 3 a 0 1 Result b Review: The Multiplexor • Selects one of the inputs to be the output, based on a control input IEC symbol of a 4-input MUX: • Lets build our logical unit using a MUX: 0 1

13. Different Implementations • Not easy to decide the “best” way to build something • Don't want too many inputs to a single gate • Don’t want to have to go through too many gates • For our purposes, ease of comprehension is important • We use multiplexors • Let's look at a 1-bit ALU for addition: • How could we build a 32-bit ALU for AND, OR and ADD? a b cin cout sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 CarryIn a Sum b CarryOut cout = a b + a cin + b cin sum = a  b  cin

14. Building a 32 bit ALU for AND, OR and ADD 1-bit ALU: We need a 4-input MUX.

15. What about subtraction (a – b) ? • Two's complement approach: just negate b and add. • A clever solution: • In a multiple bit ALU the least significant CarryIn has to be equal to 1 for subtraction.

16. Tailoring the ALU to the MIPS • Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a-b) < 0 implies a < b • Need to support test for equality (beq \$t5, \$t6, \$t7) • use subtraction: (a-b) = 0 implies a = b

17. Supporting slt • Other ALUs: • Most significant ALU:

18. 32 bit ALU supporting slt a<b  a-b<0, thus Set is the sign bit of the result.

19. Final ALU including test for equality • Notice control lines:000 = and001 = or010 = add110 = subtract111 = slt • Note: Zero is a 1 when • the result is zero!

20. Conclusion • We can build an ALU to support the MIPS instruction set • key idea: use a multiplexor to select the output we want • we can efficiently perform subtraction using two’s complement • we can replicate a 1-bit ALU to produce a 32-bit ALU • Important points about hardware • all of the gates are always working • the speed of a gate is affected by the number of inputs to the gate • the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”)

21. Conclusion • Our primary focus: comprehension, however, • clever changes to organization can improve performance(similar to using better algorithms in software) • we’ll look at examples for addition, multiplication and division

22. Problem: ripple carry adder is slow • A 32-bit ALU is much slower than a 1-bit ALU. • There are more than one way to do addition. • the two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c1 = b0c0 + a0c0 +a0b0 c2 = b1c1 + a1c1 +a1b1 c2 = c2(a0,b0,c0,a1,b1) c3 = b2c2 + a2c2 +a2b2 c3 = c3(a0,b0,c0,a1,b1,a2,b2) c4 = b3c3 + a3c3 +a3b3 c4 = c4(a0,b0,c0,a1,b1,a2,b2,a3,b3) Not feasible! Too many inputs to the gates.

23. Carry-lookahead adder • An approach in-between the two extremes • Motivation: • If we didn't know the value of carry-in, what could we do? • When would we always generate a carry? gi = ai bi • When would we propagate the carry? pi = ai + bi • Look at the truth table! • Did we get rid of the ripple?c1 = g0 + p0c0 c2 = g1 + p1c1 c2 = g1+p1g0+p1p0c0 c3 = g2 + p2c2 c3 = g2+p2g1+p2p1g0+p2p1p0c0 c4 = g3 + p3c3 c4 = ... Feasible! A smaller number of inputs to the gates.

24. Use principle to build bigger adders • Can’t build a 16 bit CLA adder (too big) • Could use ripple carry of 4-bit CLA adders • Better: use the CLA principle again! Principle shown in the figure. See textbook for details.

25. Multiplication • More complicated than addition • can be accomplished via shifting and addition • More time and more area • Let's look at 2 versions based on grammar school algorithm 0010 (multiplicand)x_1011 (multiplier) 0010 0010 0000 0010___ 0010110 • Negative numbers: • easy way: convert to positive and multiply • there are better techniques

26. Multiplication, First Version

27. Multiplication, Final Version

28. Booth’s Algorithm • The grammar school method was implemented using addition and shifting • Booth’s algorithm also uses subtraction • Based on two bits of the multiplier either add, subtract or do nothing; always shift • Handles two’s complement numbers

29. Fast multipliers • Combinational implementations • Conventional multiplier algorithm • partial products with AND gates • adders • Lots of modifications • Sequential implementations • Pipelined multiplier • registers between levels of logic • result delayed • effective speed of multiple multiplications increased

30. Four-Bit Binary Multiplication Multiplicand B3 B2 B1 B0 Multiplier  A3 A2 A1 A0 1st partial product A0B3 A0B2 A0B1 A0B0 2nd partial product A1B3 A1B2 A1B1 A1B0 3rd partial product A2B3 A2B2 A2B1 A2B0 4th partial product + A3B3 A3B2 A3B1 A3B0 Final product P7 P6 P5 P4 P3 P2 P1 P0

31. A0 & B0 A0 & B1 A0 & B2 4 A0 PP1 & / B3 4 PP2 6 / / P7:0 6 4 / PP3 / 4 PP4 / Classical Implementation

32. Pipelined Multiplier Clk / / / / / / / / / /

33. Division • Simple method: • Initialise the remainder with the dividend • Start from most significant end • Subtract divisor from the remainder if possible (quotient bit 1) • Shift divisor to the right and repeat

34. D i v i s o r S h i f t r i g h t 6 4 b i t s Q u o t i e n t 6 4 - b i t A L U S h i f t l e f t 3 2 b i t s C o n t r o l R e m a i n d e r t e s t W r i t e 6 4 b i t s Division, First Version

35. Division, Final Version Same hardware for multiply and divide.

36. Floating Point (a brief look) • We need a way to represent • numbers with fractions, e.g., 3.1416 • very small numbers, e.g., .000000001 • very large numbers, e.g., 3.15576  109 • Representation: • sign, exponent, significand: (–1)signsignificand 2exponent • more bits for significand gives more accuracy • more bits for exponent increases range • IEEE 754 floating point standard: • single precision: 8 bit exponent, 23 bit significand • double precision: 11 bit exponent, 52 bit significand

37. IEEE 754 floating-point standard • Leading “1” bit of significand is implicit • Exponent is “biased” to make sorting easier • all 0s is smallest exponent all 1s is largest • bias of 127 for single precision and 1023 for double precision • summary: (–1)signsignificand) 2exponent – bias • Example: • decimal: -.75 = -3/4 = -3/22 • binary: -.11 = -1.1 x 2-1 • floating point: exponent = 126 = 01111110 • IEEE single precision: 10111111010000000000000000000000

38. Floating-point addition 1. Shift the significand of the number with the lesser exponent right until the exponents match 2. Add the significands 3. Normalise the sum, checking for overflow or underflow 4. Round the sum