:: Final Presentation 2-D Discrete Cosine Transform

1. :: Final Presentation2-D Discrete Cosine Transform The Future Team Paradigm (Group M2): Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan Kim Project Manager: Yaping Zhan M2: Team Paradigm

2. Team Paradigm M2: Team Paradigm

3. M2: Team Paradigm

4. The Future of Technology... M2: Team Paradigm

5. Strategic Applications • High-resolution Digital Television (HDTV) • MPEG-1 and MPEG-2 • JPEG images M2: Team Paradigm

6. We notice an exponential growth of profit! :: The Concept Thinking Outside The Box M2: Team Paradigm

7. ::What is the Product? • T.A.D.A system (Targeted Advertisement Digital Ad-board) • Taxicabs serve as mobile ad unit • Each cab equipped with a digital ad board • Ad board contains GPS transmitter, HDTV satellite receiver, solar panel/battery power Thinking out of the box M2: Team Paradigm

8. ::Extended Product Measures • Target Grid System (TGS) • Central HUB Center (CHUB Center) • Joint Venture with Lucent Technologies & Bell Laboratories • Young Adults • (Gen X) • Educational Zone • Cautious Spenders M2: Team Paradigm

9. ::Marketing M2: Team Paradigm

10. M2: Team Paradigm

11. Distribution M2: Team Paradigm

12. Risks and Contingencies • Lack of specialization in this area • Partnership with Lucent Technologies • Difficulty in entering a new market • Expand company’s capabilities • Gain profit in a new market • Acquire new clients • Advantage over competitors :: What are the benefits? M2: Team Paradigm

13. How does it work? M2: Team Paradigm

14. X1 X0 x0 - x7 x0 + x7 A A A A B C -C -B A -A -A A C -B B -C A = cos(/4) X2 X3 x1 - x6 x1 + x6 = 1/2 B = cos(/8) X5 X4 x2 - x5 x2 + x5 C = sin(/8) X6 X7 x3 + x4 x3 - x4 D = cos(/16) E = cos(3/16) F = sin(3/16) D E F G E -G -D -F F -D G E G -F E -D G = sin(/16) = 1/2 Distributed algorithm of 1D DCT M2: Team Paradigm

15. X0 b015 b014…b00 A A A A B C -C -B A -A -A A C -B B -C X2 b115 b114…b10 X4 b215 b214…b20 X6 b315 b314…b30 = Distributed algorithm of 1D DCT (cont...) In two’s complement representation: ui = -buiB-1 + j=1, B-1 2-jbuij Where, buij is the jth bit, buiB-1 is the MSB, i.e. the sign bit Xn = j=1,B-1 2-jDn(bj) – Dn(bB-1), where Dn(bj) = (i=1,3Ci,nbuij) For example, D0(b14) = Ab014+Ab114+Ab214+Ab314 M2: Team Paradigm

16. R0 R7 Selector R0 R7 S1 S0 R0 R7 R5 R6 bit 1 bit 1 bit 1 bit 1 - Bit Address Generator R0 R7 Parallel to Serial 1011 Rom0 Rom7 Bit Address Generator Rom0 Rom7 Structure of 1D DCT 1D DCT Simply repeat on rows to make 2D M2: Team Paradigm

17. Data in Control logic 1D DCT (on rows) Transpose RAM 1D DCT (on columns) Data out 2D DCT Two 1D DCT can operate in pipeline to boost throughput performance, this requires RAM can be read and wrote at the same time and each 1D DCT module read/write the RAM in row and column order alternatively. M2: Team Paradigm

18. Design Process M2: Team Paradigm

19. Transistor count and performance estimation : 1DDCT module : 2DDCT = 2x1DDCT + SRAM ~ 24k M2: Team Paradigm

20. Design Process • Design Proposal • Architecture Proposal • Floorplan • Gate Level Design • Component Layout • Component Simulation • Component Layout • Chip Level Simulation • Final Design Corrections M2: Team Paradigm

21. M2: Team Paradigm

22. Da Breakdown • Key to our success was breaking down our components into individual large blocks • 1D DCT • SRAM • Further we broke down the 1D DCT • easily connected • ease in simulating, lvs'ing, drc'ing M2: Team Paradigm

23. ::Mid-Buffer • Dimensions: • 82.9u X 87.4u • Metals: • M1, M2, M3 • Directionality: • Left to Right and Down M2: Team Paradigm

24. Accumulator and P to S M2: Team Paradigm

25. Inbuffer M2: Team Paradigm

26. Sram M2: Team Paradigm

27. Sram Control M2: Team Paradigm

28. Control M2: Team Paradigm

29. Floorplan M2: Team Paradigm

30. reg reg reg reg reg reg reg reg reg reg reg reg reg reg eg reg Old floorplan proposal 150u 16bit 4x1 mux 16bit 1x4 demux 4bit 16x1 mux Sub Add 600u rom 16bit 2x1 mux 16bit 1x8 demux shift reg 16bit 4x1 mux 16bit 1x4 demux 4bit 16x1 mux Add rom Add Control logic M2: Team Paradigm

31. 16bit 4x1 mux 16bit 4x1 mux reg reg reg reg reg reg reg reg Add Add ctrl reg reg reg reg reg reg reg reg 4bit 16x1 mux 4bit 16x1 mux rom shift reg rom Add shift reg Add Floor plan Proposal 200u 500u M2: Team Paradigm

32. Layout Proposal 1D DCT Take bits 0-15 Take bits 16-32 Shift Reg R7 R0 R6 R1 R5 R2 R4 R1 MUX 4x1 32' Rom Sub DeMux 4x1 Reg 8x16' Add Add DeMux 4x1 Rom Add Control Logic approx. 220,000u 220u x 100u M2: Team Paradigm

33. 430u by 400u 2D-DCT – Floorplan (new) M2: Team Paradigm

34. Layout Size Proposal • Using a reference of an inverter • 7u x 2.5u =14u total area • Contain 2 transistors • Our design has total of approx 24k • add space for wiring • Total area estimation of around 400,000u +100,000 • =500,000u M2: Team Paradigm

35. Verification M2: Team Paradigm

36. Function 1 compare Function 2 input pass/fail Function 3 Matlab High level simulation (in C/C++) : • three implementation of 1DDCT: • Based on definition • Based on fast algorithm • Based on distributed algorithm M2: Team Paradigm

37. Step 1: R0 R7 • We begin by inputting eight, sixteen bit values into individual registers • We use a selector to select the registers that will be added and subtracted • The R0 & R7 values are added and subtracted in parallel...So forth for R1 & R6...R2 & R5....R3 & R4 • It will take 8 clock cycles to get all the data Selector R0 R7 - M2: Team Paradigm

38. Step 1 (Verilog) always @ (posedge clk or negedge rst) begin if(rst==0) begin count <= 0; end else begin if(in_clr==1) begin count <= 0; end else begin if(in_valid && ~out_full) begin buf[count] <= in_data; count <= count + 1; end end end end // always @ (posedge clk or negedge rst) always @ (posedge clk) begin if(in_read) begin out_data1 <= buf[in_addr]; out_data2 <= buf[7-in_addr]; end end Write operation Read operation M2: Team Paradigm

39. Step 2 bit 1 bit 1 bit 1 bit 1 R0 R7 1011 Bit Address Generator Rom0 Rom7 • Store the results from the addition and subtraction into 8, 16' registers • Taking the first bit in each of the four registers (addition results and subtraction result) we use the value to allow the bit address generator to store it in the proper position in ROM M2: Team Paradigm

40. Step 2 (Verilog) always @ (posedge clk or negedge rst) begin if(rst==0) begin count <= 0; end else begin if(in_clr==1) begin count <= 0; end else begin if(in_read & ~out_full) begin buf[count] <= in_data; count <= count + 1; end end end end always @ (in_bitpos) begin out_addr[3] <= buf[0][in_bitpos:in_bitpos]; out_addr[2] <= buf[1][in_bitpos:in_bitpos]; out_addr[1] <= buf[2][in_bitpos:in_bitpos]; out_addr[0] <= buf[3][in_bitpos:in_bitpos]; end Read operation Bit address generator M2: Team Paradigm

41. Step 3 • From the ROM the data in the addresses are added, stored in a register then the result is shifted (multiplied by a factor of two...two's complement) Rom0 Rom7 S1 S0 R5 R6 Parallel to Serial M2: Team Paradigm

42. Step 3 (Verilog) always @ (posedge clk or negedge rst) begin if(rst==0) begin out_data <= 0; bit_pos <= 15; end else begin if(in_clr==1) begin out_data <= 0; bit_pos <= 15; end else begin if(~out_done) begin out_data <= out_data + in_data; bit_pos <= bit_pos - 1; end end // else: !if(in_clr==1) end end M2: Team Paradigm

43. C Code Result M2: Team Paradigm

44. Verilog Verification - 189c, ef9c M2: Team Paradigm

45. Schematic Verification - 189c, ef9c M2: Team Paradigm

46. Layout M2: Team Paradigm

47. Poly and Active M1 1D-DCT M2: Team Paradigm

48. M4 M3 M2 M2: Team Paradigm

49. 2D-DCT M2: Team Paradigm

50. LVS M2: Team Paradigm