Gauri Kulkarni Graduate Project Presentation Dept. Of Electrical Engineering, San Jose State University.
Comparison of two logic techniques in a High Speed Frequency Divider/Prescalar TSPC Technique and Two phase Clocking Technique
Objective • To compare two logic techniques using D Flip-Flops in a High Speed dynamic Prescalar. • Analyze the performance in terms of Speed, Area, Ease of implementation and Design and Power consumption. • Techniques used-TSPC and Two Phase Clocking Scheme.
Introduction:Frequency Synthesizer • 3 types: ÷ by 2 counter, Dual modulus Prescalar, divide by N counter • ÷ by 2 has highest operating frequency, limited as divide by 2*M stages • Dual Modulus-next high frequency as load is low. Ratio of N/N+1 • Divide by N -N arbitrary
Introduction - continued…. • Prescalar/frequency divider consists of a synchronous counter, an asynchronous counter and a modulus control circuit. • Many logic styles available; Standard Dynamic,NORA,ZIPPER,DOMINO, TSPC and Two phase clocking, DCVSL,CPL,CVSL etc. • Comparison of TSPC and two phase clocking scheme
Consists of resistive load type pull up and pull down network Small pull-up than static gate pull down longer as pull up is fighting Pseudo NMOS Logic Vdd a b gnd
Pseudo Inverters clk D O/P O/P O/P D clk clk clk D D O/P Pseudo-PMOS Pseudo-NMOS N-CMOS P-CMOS inverter inverter
TSPC technique • Consists of Precharge and Evaluate with a single clock signal • Easier to route • No clock skew • Fast • Original DFF based on P-C²MOS, N precharge, N-C²MOS stages • New fast DFF based on pseudo-NMOS,N-precharge and pseudo-PMOS inverter