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Network On Chip Cache Coherency. Final report, part B Students: Zemer Tzach Kalifon Ethan Instructor: Walter Isaschar Winter 2009. Agenda. General concepts. Description of the coherency protocol. Architecture design. Components implementation. Simulations.

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Network on chip cache coherency

Network On Chip Cache Coherency

Final report, part B

Students:ZemerTzach

Kalifon Ethan

Instructor: Walter Isaschar

Winter 2009


Agenda
Agenda

  • General concepts.

  • Description of the coherency protocol.

  • Architecture design.

  • Components implementation.

  • Simulations.

  • Functionality demonstration .

Network On Chip - Cache Coherency


General concepts

General Concepts

Network On Chip - Cache Coherency


General background
General Background

  • Modern CPU’s are based on CMP – Chip-Multi Processor.

  • Improved performance is achieved by “Distribution and Parallelism”.

  • Cores interact by using NoC – Network on Chip.

Network On Chip - Cache Coherency


Noc general diagram
NoC General Diagram

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5


Noc characteristics
NoC Characteristics

Wormhole packet routing.

Packet’s path is X-Y.

Units can communicate simultaneously.

Reduce power consumption.

Scalability.

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6


Cache coherency
Cache Coherency

Cache: On chip fast temporary storage.

Cache Coherency: CMP cores use only up to date data.

Traditionally, Cache Coherency achieved by central memory control unit.

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7


Traditionally cache coherency
Traditionally Cache Coherency

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8


Problem description
Problem Description

  • Prior Cache Coherency protocols are irrelevant – NoC doesn’t have central unit.

  • Adding such unit will damage both NoC’s scalability and parallelism.

Network On Chip - Cache Coherency


Solution requirements
Solution Requirements

  • High performance:

    • Avoid “Hot Spots” and “Bottlenecks”.

  • Minimize resources.

  • Won’t affect main NoC characteristics (e.g. scalability).

Network On Chip - Cache Coherency


Solution basics
Solution Basics

  • Memory control distribution according to memory spaces.

  • Placement of control units as part of the NoC.

Network On Chip - Cache Coherency


Solution diagram
Solution Diagram

Network On Chip - Cache Coherency


Solution general example
Solution General Example

  • CPU refer to the appropriate Controller.

  • Controller order transfer of data.

  • Other CPU sends the cache line.

  • Read Miss on line 1000.

Network On Chip - Cache Coherency


Project goal
Project Goal

  • Design and implement Cache Coherency protocol for CMP based NoC.

    • Implement NoC (part one).

    • Implement Cache Coherency support for NoC (part two).

Network On Chip - Cache Coherency


Coherency protocol

Coherency Protocol

Network On Chip - Cache Coherency


General description
General Description

  • Three types of transactions: Read, Read for Ownership and Invalidation.

  • Cache line’s status can be I/S/E (Invalid/Shared/Exclusive respectively).

  • Each cache control unit keeps journal which determines line’s status.

  • Requests are first addressed to the appropriate cache control unit.

Network On Chip - Cache Coherency


Protocol s terminology
Protocol’s Terminology

  • Requester.

  • Home Node.

  • Closest Sharer.

  • Owner.

Network On Chip - Cache Coherency


Read miss line is shared
Read Miss: Line is Shared

Network On Chip - Cache Coherency


Write miss line is shared
Write Miss: Line is Shared

Network On Chip - Cache Coherency


Design difficulties 1 st example
Design difficulties (1st example)

Network On Chip - Cache Coherency


Design difficulties 2 nd example
Design difficulties (2nd example)

Network On Chip - Cache Coherency


Protocol s features
Protocol’s Features

  • Parallel handling of Read requests.

  • Data is forwarded by the Closest Sharer.

  • Transparency: any CPU which uses M/E/S/I is supported.

  • The protocol supports strongly consistent processors.

Network On Chip - Cache Coherency


Architecture

Architecture

Network On Chip - Cache Coherency


Cmp diagram
CMP Diagram

Network On Chip - Cache Coherency


Cpu node structure
CPU Node Structure

Network On Chip - Cache Coherency


Noc interface
NoC Interface

  • Functions as a gateway to the NoC.

  • Packing/unpacking flits into/from NoC’s Packets.

  • Transmit and receive data simultaneously.

Network On Chip - Cache Coherency


Noc interface structure
NoC Interface Structure

Network On Chip - Cache Coherency


Cpu interface
CPU Interface

  • Adapting between NoC’s Cache Coherency Protocol and the CPU.

  • Translating NoC’s Packets into/from FSB transactions.

  • CPU transactions doesn’t prevent the CPU Interface from handling the Protocol’s packets.

Network On Chip - Cache Coherency


Cpu interface structure
CPU Interface Structure

Network On Chip - Cache Coherency


Controller node structure
Controller Node Structure

Network On Chip - Cache Coherency


Cache coherency controller
Cache Coherency Controller

  • Manages the Coherency Protocol.

  • Each CCC (Cache Coherency Controller) is responsible for a specific set of the Memory Lines.

  • The Directory Table (DT) holds the status of the above Lines as well as several protocol’s information bits.

Network On Chip - Cache Coherency


Ccc structure
CCC Structure

Network On Chip - Cache Coherency


Dt general structure
DT General Structure

  • The DT will contain the following data for each Line:

Network On Chip - Cache Coherency


Architecture features
Architecture Features

  • Message’s length vary according to its purpose. Reduces NoC’s congestion.

  • Messages carry the transaction information (reduces HW requirements).

  • Transaction can be blocked by memory update only (allows high parallelism).

  • Scalable.

Network On Chip - Cache Coherency


Cmp implementation

CMPImplementation

Network On Chip - Cache Coherency


Cmp characteristics
CMP Characteristics

  • Size of memory unit is 1 [Byte].

  • Cache line comprise 2 memory units (can be enlarged).

  • Size of memory is 16 [Byte].

  • CPU’s actions are determined by the user.

Network On Chip - Cache Coherency


Cpu implementation
CPU Implementation

Network On Chip - Cache Coherency


Cpu node implementation
CPU Node Implementation

Network On Chip - Cache Coherency


Ccc node implementation
CCC Node Implementation

Network On Chip - Cache Coherency


Cmp implementation1
CMP Implementation

Network On Chip - Cache Coherency


Synthesis parameters
Synthesis Parameters

Network On Chip - Cache Coherency


System performance
System Performance

  • System’s clock frequency is 100 [MHz].

  • CPU’s hold-up (in cycles):

Network On Chip - Cache Coherency


System performance1
System Performance

  • M – Memory penalty.

  • C – Dependant on number of CPUs.

  • Delay in all nodes is one/two cycle.

  • In larger systems network factor becomes greater.

Network On Chip - Cache Coherency


Cmp simulations

CMPSimulations

Network On Chip - Cache Coherency


Read miss line is shared 1
Read Miss: Line is Shared (1)

  • CPU1x1 reads cache line. The appropriate line is stored in CPU0x0.

2

1

Network On Chip - Cache Coherency


Read miss line is shared 2
Read Miss: Line is Shared (2)

2

3

4

1

Network On Chip - Cache Coherency


Read miss line is shared 3
Read Miss: Line is Shared (3)

2

6

1

5

Network On Chip - Cache Coherency


Read miss line is exclusive 1
Read Miss: Line is Exclusive (1)

  • CPU1x1 reads for ownership. The appropriate line is stored in CPU0x0.

2

2

1

1

Network On Chip - Cache Coherency


Read miss line is exclusive 2
Read Miss: Line is Exclusive (2)

2

3

1

4

Network On Chip - Cache Coherency


Read miss line is exclusive 3
Read Miss: Line is Exclusive (3)

2

5

1

Network On Chip - Cache Coherency


Read miss line is exclusive 4
Read Miss: Line is Exclusive (4)

2

7

1

6

Network On Chip - Cache Coherency


Demonstration

Demonstration

Network On Chip - Cache Coherency


Demonstration diagram
Demonstration Diagram

Network On Chip - Cache Coherency


Tasks part a
Tasks – Part A

  • Familiarize with design tools.

  • Familiarize with VirtexII Pro FPGA (application & components).

  • Design & Implement NoC’s router.

  • Assemble NoC (2x2 grid) using our router implementation.

Network On Chip - Cache Coherency


Tasks part b
Tasks – Part B

  • Design Cache Coherency protocol for CMP based on faculty research.

  • Assemble CMP based on our NoC.

  • Implement the protocol as part of the assembled CMP.

Network On Chip - Cache Coherency


Future work
Future Work

  • Memory should be distributed.

  • Improve NoC Interface latency.

  • Messages carry all the transaction’s information.

  • Strongly consistent processors.

Network On Chip - Cache Coherency


Conclusions 1
Conclusions (1)

  • All architectural goals were achieved.

  • Minimal HW utilization makes for practical solution.

  • The most efficient possible by protocol definition.

Network On Chip - Cache Coherency


Conclusions 2
Conclusions (2)

  • The generic design makes a great basis for further studies and research.

  • With larger systems, the project advantages would be even more predominant.

Network On Chip - Cache Coherency