Network On Chip Cache Coherency

1. Network On Chip Cache Coherency Final report, part B Students:ZemerTzach Kalifon Ethan Instructor: Walter Isaschar Winter 2009

2. Agenda • General concepts. • Description of the coherency protocol. • Architecture design. • Components implementation. • Simulations. • Functionality demonstration . Network On Chip - Cache Coherency

3. General Concepts Network On Chip - Cache Coherency

4. General Background • Modern CPU’s are based on CMP – Chip-Multi Processor. • Improved performance is achieved by “Distribution and Parallelism”. • Cores interact by using NoC – Network on Chip. Network On Chip - Cache Coherency

5. NoC General Diagram Network On Chip - Cache Coherency 5

6. NoC Characteristics Wormhole packet routing. Packet’s path is X-Y. Units can communicate simultaneously. Reduce power consumption. Scalability. Network On Chip - Cache Coherency 6

7. Cache Coherency Cache: On chip fast temporary storage. Cache Coherency: CMP cores use only up to date data. Traditionally, Cache Coherency achieved by central memory control unit. Network On Chip - Cache Coherency 7

8. Traditionally Cache Coherency Network On Chip - Cache Coherency 8

9. Problem Description • Prior Cache Coherency protocols are irrelevant – NoC doesn’t have central unit. • Adding such unit will damage both NoC’s scalability and parallelism. Network On Chip - Cache Coherency

10. Solution Requirements • High performance: • Avoid “Hot Spots” and “Bottlenecks”. • Minimize resources. • Won’t affect main NoC characteristics (e.g. scalability). Network On Chip - Cache Coherency

11. Solution Basics • Memory control distribution according to memory spaces. • Placement of control units as part of the NoC. Network On Chip - Cache Coherency

12. Solution Diagram Network On Chip - Cache Coherency

13. Solution General Example • CPU refer to the appropriate Controller. • Controller order transfer of data. • Other CPU sends the cache line. • Read Miss on line 1000. Network On Chip - Cache Coherency

14. Project Goal • Design and implement Cache Coherency protocol for CMP based NoC. • Implement NoC (part one). • Implement Cache Coherency support for NoC (part two). Network On Chip - Cache Coherency

15. Coherency Protocol Network On Chip - Cache Coherency

16. General Description • Three types of transactions: Read, Read for Ownership and Invalidation. • Cache line’s status can be I/S/E (Invalid/Shared/Exclusive respectively). • Each cache control unit keeps journal which determines line’s status. • Requests are first addressed to the appropriate cache control unit. Network On Chip - Cache Coherency

17. Protocol’s Terminology • Requester. • Home Node. • Closest Sharer. • Owner. Network On Chip - Cache Coherency

18. Read Miss: Line is Shared Network On Chip - Cache Coherency

19. Write Miss: Line is Shared Network On Chip - Cache Coherency

20. Design difficulties (1st example) Network On Chip - Cache Coherency

21. Design difficulties (2nd example) Network On Chip - Cache Coherency

22. Protocol’s Features • Parallel handling of Read requests. • Data is forwarded by the Closest Sharer. • Transparency: any CPU which uses M/E/S/I is supported. • The protocol supports strongly consistent processors. Network On Chip - Cache Coherency

23. Architecture Network On Chip - Cache Coherency

24. CMP Diagram Network On Chip - Cache Coherency

25. CPU Node Structure Network On Chip - Cache Coherency

26. NoC Interface • Functions as a gateway to the NoC. • Packing/unpacking flits into/from NoC’s Packets. • Transmit and receive data simultaneously. Network On Chip - Cache Coherency

27. NoC Interface Structure Network On Chip - Cache Coherency

28. CPU Interface • Adapting between NoC’s Cache Coherency Protocol and the CPU. • Translating NoC’s Packets into/from FSB transactions. • CPU transactions doesn’t prevent the CPU Interface from handling the Protocol’s packets. Network On Chip - Cache Coherency

29. CPU Interface Structure Network On Chip - Cache Coherency

30. Controller Node Structure Network On Chip - Cache Coherency

31. Cache Coherency Controller • Manages the Coherency Protocol. • Each CCC (Cache Coherency Controller) is responsible for a specific set of the Memory Lines. • The Directory Table (DT) holds the status of the above Lines as well as several protocol’s information bits. Network On Chip - Cache Coherency

32. CCC Structure Network On Chip - Cache Coherency

33. DT General Structure • The DT will contain the following data for each Line: Network On Chip - Cache Coherency

34. Architecture Features • Message’s length vary according to its purpose. Reduces NoC’s congestion. • Messages carry the transaction information (reduces HW requirements). • Transaction can be blocked by memory update only (allows high parallelism). • Scalable. Network On Chip - Cache Coherency

35. CMPImplementation Network On Chip - Cache Coherency

36. CMP Characteristics • Size of memory unit is 1 [Byte]. • Cache line comprise 2 memory units (can be enlarged). • Size of memory is 16 [Byte]. • CPU’s actions are determined by the user. Network On Chip - Cache Coherency

37. CPU Implementation Network On Chip - Cache Coherency

38. CPU Node Implementation Network On Chip - Cache Coherency

39. CCC Node Implementation Network On Chip - Cache Coherency

40. CMP Implementation Network On Chip - Cache Coherency

41. Synthesis Parameters Network On Chip - Cache Coherency

42. System Performance • System’s clock frequency is 100 [MHz]. • CPU’s hold-up (in cycles): Network On Chip - Cache Coherency

43. System Performance • M – Memory penalty. • C – Dependant on number of CPUs. • Delay in all nodes is one/two cycle. • In larger systems network factor becomes greater. Network On Chip - Cache Coherency

44. CMPSimulations Network On Chip - Cache Coherency

45. Read Miss: Line is Shared (1) • CPU1x1 reads cache line. The appropriate line is stored in CPU0x0. 2 1 Network On Chip - Cache Coherency

46. Read Miss: Line is Shared (2) 2 3 4 1 Network On Chip - Cache Coherency

47. Read Miss: Line is Shared (3) 2 6 1 5 Network On Chip - Cache Coherency

48. Read Miss: Line is Exclusive (1) • CPU1x1 reads for ownership. The appropriate line is stored in CPU0x0. 2 2 1 1 Network On Chip - Cache Coherency

49. Read Miss: Line is Exclusive (2) 2 3 1 4 Network On Chip - Cache Coherency

50. Read Miss: Line is Exclusive (3) 2 5 1 Network On Chip - Cache Coherency