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N. Fasarakis, A. Tsormpatzoglou, D. H. Tassis, K. Papathanasiou,

Compact Modeling of Nanoscale FinFETs for Circuit Simulators. N. Fasarakis, A. Tsormpatzoglou, D. H. Tassis, K. Papathanasiou, G. Ghibaudo * and C. A. Dimitriadis Aristotle University of Thessaloniki, Department of Physics, Greece * IMEP, MINATEC, Grenoble, France. Why FinFETs.

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N. Fasarakis, A. Tsormpatzoglou, D. H. Tassis, K. Papathanasiou,

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  1. Compact Modeling of Nanoscale FinFETs for Circuit Simulators N. Fasarakis, A. Tsormpatzoglou, D. H. Tassis, K. Papathanasiou, G. Ghibaudo* and C. A. Dimitriadis Aristotle University of Thessaloniki, Department of Physics, Greece *IMEP, MINATEC, Grenoble, France

  2. Why FinFETs Better electrostatic control suppress of the SCEs, steeper subthreshold slope Fully depleted channel higher on-current, faster carrier transport Undoped or lightly doped channel  reduced dopant fluctuation  no variability In practice, more feasible is the the fabrication of TG FinFETs

  3. Intel’s FinFETs are less fin and more trapezoidal or triangle

  4. Main achievements 1. Novel analytical compact drain current and trans-capacitances models suitable to ultra-scaled DG FinFETs were developed. 2. The analytical compact models of DG FinFETs have been extended to rectangular TG FinFETs. 3. The analytical compact models of rectangular TG FinFETs have been extended to TG FinFETs with non-vertical sidewalls (trapezoidal & triangular). 4. The analytical compact models of DG FinFETs have been extended to tetragonal MOSFETs and then to cylindrical GAA MOSFETs.

  5. Cross-section configuration of FinFETs

  6. Threshold voltage:  Subthreshold slope:  Subthreshold swing coefficient: Step 1: Analytical parameters of DG FinFETs Fasarakis et al., Solid State Electronics 64, 34, 2011.

  7. Step 2: Compact Drain Current Model for DG FinFETs Channel length modulation L (eff, VE) Mobility degradation eff (o, 1,0, Rsd, sat ) Quantum-mechanical effects Vt (Vt shift) Papathanasiou et. al., Solid State Electronics 69, p. 55, 2011.

  8. TG FinFET L=40 nm, Hfin=20 nm, Wfin=20 nm TCAD results for DG FinFET Δφ=0,θ1,0=0,μo=200 cm2/Vs, RsdWfin=2.710-4 Ωcm, c1=2, VE=0.05 V

  9. Step 3: Drain current compact model for TG FinFETs The model of DG FinFETs is extended to TG FinFETs by capturing the electrostatic control of the top gate over the SCEs 1. Correction of the threshold voltage 2. Correction of the subthreshold swing coefficient 3. Correction of the effective gate length Weff Fasarakis et al., IEEE Trans. Electron Dev. 59, 1891, 2012.

  10. TG FinFET L=40 nm, Hfin=20 nm, Wfin=20 nm TCAD results for TG FinFETs

  11. Step 4: Trans-capacitances of TG FinFETs A. Capacitance modeling in sub-threshold Mobile charge negligible  capacitive coupling between gate electrodes B. Capacitance modeling in weak to strong inversion Fasarakis et al., IEEE Trans. Electron Devices, in press, 2012

  12. L=20 nm, Hfin=20 nm, Wfin=10 nm TCAD results from rectangular TG FinFETs

  13. Step 5: Compact modeling of non-vertical sidewall TG FinFETs Concept: Introduce the equivalent device parameters i) Equivalent fin-width: Trapezoidal cross-section Triangular cross-section (Wfin,top=0) ii) Equivalent channel-width: iii) Device parameters (Vt, eff, SS)

  14. TCAD results for trapezoidal FinFET Hfin=30nm, Wfin,bottom=15nm, L=25nm, tox=1nm, o=200cm2/Vs, 1=0, =0

  15. TCAD results for triangular FinFET Hfin=30nm, Wfin,bottom=15nm, L=25nm, tox=1nm, o=200cm2/Vs, 1=0, =0

  16. Step 6: Compact modeling of cylindrical GAA MOSFETs Equivalent device parameters

  17. Example: Drain current in CGAA MOSFETs

  18. Example: Trans-capacitances in CGAA MOSFETs

  19. The statistical variability and reliability of nanoscale FinFETs can be easily captured Manufacturing Variability

  20. The compact model for nano-scale MOSFETs is complete, satisfies all cross-section geometrical configurations (DG, TG, GAA) and thus it can be implemented for the development of commercial simulation tools Concluding Remark

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