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Bit-Slicing in Cadence

Bit-Slicing in Cadence. Evan Vaughan. What I’m Trying to Do. No native support for bit-slicing in Cadence Synthesis Tools Synopsys does provide this Trick RTL Compiler and Soc Encounter into laying out and Adder in a bit slice Use 4 bit Kogge -Stone adder as test design. Initial Synthesis.

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Bit-Slicing in Cadence

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  1. Bit-Slicing in Cadence Evan Vaughan

  2. What I’m Trying to Do • No native support for bit-slicing in Cadence Synthesis Tools • Synopsys does provide this • Trick RTL Compiler and Soc Encounter into laying out and Adder in a bit slice • Use 4 bit Kogge-Stone adder as test design

  3. Initial Synthesis • Reduce Nangate library to only necessary components • and, or, inv, xor, aoi21 • Very disordered layout

  4. Initial Synthesis Placement

  5. Second Attempt • Made no modifications to Nangate library • Want Generate/Propagate blocks to be in order on, on top row

  6. Third Try • Synthesized netlist created 4 different instantiations of a half-adder (GPGenerator) and placed them separately • I edited synthesized netlist to have one large instantiation that would be called once.

  7. no change.

  8. Fourth (current) Method • Create a new library using modified Nangate components • Combine four half-adder blocks into one large standard cell • Determine what other components can be combined later • Requires layout and schematic views

  9. Problems encountered • Viewing layouts • Couldn’t directly open .oa layouts in virtuoso • Got around this by “streaming” GDSII layout versions • Schematics • PNG and .edif views • Based schematic off PNG, failed LVS • Couldn’t import .edif • Read through .edif and found that Nangate uses low threshold models • Still failed LVS (no power or ground connections)

  10. Continued…. • Because just four blocks combined, can just edit .lib and .lef files by hand to create new cells • Shouldn’t be great performance difference between single block and four combined blocks

  11. Questions/Suggestions

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