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CPU08 INSTRUCTION SET

CPU08 INSTRUCTION SET. INSTRUCTION SET. Data Movement Arithmetic Logical Data Manipulation Bit Manipulation Program Control Binary Coded Decimal Special. Data Movement - Load CPU Registers -. Source . Effect on CCR . Address . Bus. Forms . Description . Operation .

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CPU08 INSTRUCTION SET

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  1. CPU08INSTRUCTIONSET

  2. INSTRUCTION SET • Data Movement • Arithmetic • Logical • Data Manipulation • Bit Manipulation • Program Control • Binary Coded Decimal • Special

  3. Data Movement- Load CPU Registers - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles LDA #opr IMM 2 LDA opr DIR 3 LDA opr EXT 4 Load LDA opr,X IX2 4 Accumulator A <— (M) 0 – – ³ ³ – LDA opr,X IX1 3 from Memory LDA ,X IX 2 LDA opr,SP SP1 4 opr,SP LDA SP2 5 LDX #opr IMM 2 LDX opr DIR 3 LDX opr EXT 4 Load Index LDX opr,X IX2 4 Register X X <— (M) 0 – – ³ ³ – LDX opr,X IX1 3 from Memory LDX ,X IX 2 LDX opr,SP SP1 4 LDX opr,SP SP2 5 Load Index LDHX #opr IMM 3 Register H:X H:X <— (M:M + 1) 0 – – ³ ³ – LDHX opr DIR 4 from Memory

  4. Data Movement- Store CPU Registers - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles STA opr DIR 3 STA opr EXT 4 STA opr,X Store IX2 4 STA opr,X Accumulator in M <— (A) 0 – – ³ ³ – IX1 3 STA ,X Memory IX 2 STA opr,SP SP1 4 STA opr,SP SP2 5 STX opr DIR 3 STX opr EXT 4 STX opr,X Store Index IX2 4 STX opr,X Register X in M <— (X) 0 – – ³ ³ – IX1 3 STX ,X Memory IX 2 STX opr,SP SP1 4 STX opr,SP SP2 5 Store Index STHX opr Register H:X in M:M+1 <— (H:X) 0 – – ³ ³ – DIR 4 Memory

  5. Data Movement- Stack Operations - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles Push Accumulator PSHA Push (A); SP <— (SP – $01) – – – – – – INH 2 onto Stack Push Index Register PSHH Push (H); SP <— (SP – $01) – – – – – – INH 2 H onto Stack Push Index Register PSHX Push (X); SP <— (SP – $01) – – – – – – INH 2 X onto Stack Pull Accumulator PULA SP <— (SP + $01); Pull (A) – – – – – – INH 2 from Stack Pull Index Register PULH SP <— (SP + $01); Pull (H) – – – – – – INH 2 H from Stack Pull Index Register PULX SP <— (SP + $01); Pull (X) – – – – – – INH 2 X from Stack

  6. Data Movement- Register to Register - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles Transfer Accumulator TAP CCR <— (A) ³ ³ ³ ³ ³ ³ INH 2 to CCR Transfer CCR to TPA A <— (CCR) – – – – – – INH 1 Accumulator Transfer Accumulator TAX X <— (A) – – – – – – INH 1 to Index Register X Transfer Index Register TXA A <— (X) – – – – – – INH 1 X to Accumulator Transfer Index TXS SPH:SP <— (H:X) – $0001 – – – – – – INH 2 Register to SP Transfer SP to TSX H:X <— (SPH:SP) + $0001 – – – – – – INH 2 Index Register

  7. Data Movement- Memory to Memory - • See Addressing Modes, Memory to Memory, for MOV instruction usage notes. Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles MOV opr,opr DD 5 (M) <— (M) Destination Source MOV opr,X+ DIX+ 4 Move 0 – – ³ ³ – MOV #opr,opr IMD 4 H:X <— (H:X) + 1 in X+ modes MOV X+,opr IX+D 4

  8. Arithmetic- Addition - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles ADD #opr IMM 2 ADD opr DIR 3 ADD opr EXT 4 Add Memory to ADD opr,X IX2 4 Accumulator A <— (A) + (M) ³ ³ – ³ ³ ³ ADD opr,X IX1 3 without Carry ADD ,X IX 2 ADD opr,SP SP1 4 ADD opr,SP SP2 5 ADC #opr IMM 2 ADC opr DIR 3 ADC opr EXT 4 Add Memory to ADC opr,X IX2 4 Accumulator A <— (A) + (M) + (C) ³ ³ – ³ ³ ³ ADC opr,X IX1 3 with Carry ADC ,X IX 2 ADC opr,SP SP1 4 ADC opr,SP SP2 5

  9. Arithmetic- Subtraction - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles SUB #opr IMM 2 SUB opr DIR 3 SUB opr EXT 4 Subtract SUB opr,X IX2 4 Memory from A <— (A) – (M) ³ – – ³ ³ ³ SUB opr,X IX1 3 Accumulator SUB ,X IX 2 without Carry SUB opr,SP SP1 4 SUB opr,SP SP2 5 SBC #opr IMM 2 SBC opr DIR 3 SBC opr EXT 4 Subtract SBC opr,X IX2 4 Memory from A <— (A) – (M) – (C) ³ – – ³ ³ ³ SBC opr,X IX1 3 Accumulator SBC ,X IX 2 with Carry SBC opr,SP SP1 4 SBC opr,SP SP2 5

  10. Arithmetic- Multiplication & Division - • MUL • X will contain the MSB of product • A will contain the LSB of product • DIV • H is MSB of dividend • A is LSB of dividend • X is unaffected Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles Unsigned MUL 8-bit x 8-bit X:A <— (X) x (A) – 0 – – – 0 INH 5 Multiply Unsigned A <— (H:A) ÷ (X) DIV 16-bit x 8-bit – – – – ³ ³ INH 7 Divide H <— Remainder

  11. Arithmetic- Increment & Decrement - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles INC opr M <— (M) + 1 DIR 4 INCA A <— (A) + 1 INH 1 INCX X <— (X) + 1 INH 1 Increment ³ – – ³ ³ – INC opr,X M <— (M) + 1 IX1 4 INC ,X M <— (M) + 1 IX 3 INC opr,SP M <— (M) + 1 SP1 5 DEC opr M <— (M) – 1 DIR 4 DECA A <— (A) – 1 INH 1 DECX X <— (X) – 1 INH 1 Decrement ³ – – ³ ³ – DEC opr,X M <— (M) – 1 IX1 4 DEC ,X M <— (M) – 1 IX 3 DEC opr,SP M <— (M) – 1 SP1 5

  12. LOOP D = Delay = 500 uSec BNE LOOP and then exits the loop. DONE BRA DONE Write your program here: F = Frequency = 8 MHz CPU Internal Bus Frequency Total # of loop iterations = 4 x 10 E3 ÷ ____ = ______ Total # of clocks = F x D = (8 x 10 E6) x (500 x 10 E-6) = 4 x 10 E3 2. Decrement counter. 500 uSec Delay Routine Exercise 4. Done, return to caller. Write a 500 microsecond delay routine. The routine loops until 500 microseconds has expired 1. Initialize counter to 500 uSec delay value. Suggested program steps: 3. If counter  zero, goto step 2, else goto step 4. (execution time): Number of clocks HC05-Dly500uSecExer

  13. Arithmetic- Complement & Negation - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles • One’s Complement • Unsigned operation • Two’s Complement • Signed operation COM opr M <— $FF – (M) DIR 4 COMA A <— $FF – (A) INH 1 Complement COMX X <— $FF – (X) INH 1 (One's 0 – – ³ ³ 1 COM opr,X M <— $FF – (M) IX1 4 Complement ) COM ,X M <— $FF – (M) IX 3 COM opr,SP M <— $FF – (M) SP1 5 NEG opr M <— $00 – (M) DIR 4 NEGA A <— $00 – (A) INH 1 Negate NEGX X <— $00 – (X) INH 1 (Two's ³ – – ³ ³ ³ NEG opr,X M <— $00 – (M) IX1 4 Complement ) NEG ,X M <— $00 – (M) IX 3 NEG opr,SP M <— $00 – (M) SP1 5

  14. Arithmetic- Comparison - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles CMP #opr IMM 2 CMP opr DIR 3 CMP opr EXT 4 Compare CMP opr,X IX2 4 Accumulator A – (M) ³ – – ³ ³ ³ CMP opr,X IX1 3 with Memory CMP ,X IX 2 CMP opr,SP SP1 4 CMP opr,SP SP2 5 CPX #opr IMM 2 CPX opr DIR 3 CPX opr EXT 4 Compare Index CPX opr,X IX2 4 Register X with X – (M) ³ – – ³ ³ ³ CPX opr,X IX1 3 Memory CPX ,X IX 2 CPX opr,SP SP1 4 CPX opr,SP SP2 5 Compare Index CPHX #opr IMM 3 Register H:X H:X – (M:M + 1) ³ – – ³ ³ ³ CPHX opr DIR 4 with Memory

  15. Arithmetic- Miscellaneous - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles CLR opr M <— $00 DIR 3 CLRA A <— $00 INH 1 CLRX X <— $00 INH 1 CLRH Clear H <— $00 0 – – 0 1 – INH 1 CLR opr,X M <— $00 IX1 3 CLR ,X M <— $00 IX 2 CLR opr,SP M <— $00 SP1 4 TST opr (M) – $00 DIR 3 TSTA (A) – $00 INH 1 Test for TSTX (X) – $00 INH 1 Negative or 0 – – ³ ³ – TST opr,X (M) – $00 IX1 3 Zero TST ,X (M) – $00 IX 2 TST opr,SP (M) – $00 SP1 4 Add Immediate AIS #opr Value (Signed) to SPH:SP <— (SPH:SP) + (16 << M) – – – – – – IMM 2 Stack Pointer Add Immediate AIX #opr Value (Signed) to H:X <— (H:X) + (16 << M) – – – – – – IMM 2 Index Register H:X

  16. Block Move Routine Exercise Write a Block Move routine. The routine copies data bytes starting from memory location $0140 to memory starting at $0050 until a data byte with a value of zero is moved. Write your program here: Suggested program steps: ORG $140 Originate data at address $140 SOURCE FCC 'Hello! World' Form table of data to be moved FCB 0 Form Constant Byte of value = 0 DEST EQU $50 Destination start address is $50 ORG $6E00 Originate program at address $6E00 1. Clear the X register. LOOP 2. Fetch data byte from source address. 3. Write data byte to destination address. BEQ DONE 4. If data byte moved = zero, go to 7, else goto 5. 5. Increment X pointer to next byte location. BRA LOOP 6. Go to step 2. DONE BRA DONE 7. Done, stay here. HC08-BlkMovExer

  17. 00F7 X X SP temp 1 AIS #-6 temp 2 msb temp 2 lsb temp 3 AIS #6 temp 4 temp 5 SP PC msb 00FF PC lsb More on AIS • AIS can be used to quickly allocate or deallocate stack space • Temporary variables • Procedure frames SUB1 AIS #-6 ;Allocate 6 bytes • • AIS #6 ;Deallocate 6 bytes RTS

  18. More on AIX • AIX can be used: • Efficiently increment or decrement the H:X register • INCX / DECX only affect the X register • INCX / DECX affect the CCR, AIX does not • Looping over blocks of memory • Indexed addressing with post increment only increments • Only available for MOV and CBEQ instructions

  19. AIX Example * Find 8 bit checksum for a 512 byte table ORG $0100 TABLE RMB 512 ;Table of data locations ORG $6E00 LDHX #511 ;Initialize byte counter CLRA ;Initialize checksum ADDLOOP ADD Table,X ;Calculate checksum AIX #-1 ;Decrement byte counter *DECX would not carry from X through H. AIX will. CPHX #0 ;Done? * CPHX sets CCR bits. DECX would have. AIX does not. BPL ADDLOOP ;Loop if not complete

  20. Logical Operators Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles AND #opr IMM 2 AND opr DIR 3 AND opr EXT 4 Logical AND AND opr,X IX2 4 Accumulator A <— (A) L (M) 0 – – ³ ³ – AND opr,X IX1 3 and Memroy AND ,X IX 2 AND opr,SP SP1 4 AND opr,SP SP2 5 ORA #opr IMM 2 ORA opr DIR 3 ORA opr EXT 4 Inclusive OR ORA opr,X IX2 4 Accumulator A <— (A) + (M) 0 – – ³ ³ – ORA opr,X IX1 3 and Memory ORA ,X IX 2 ORA opr,SP SP1 4 ORA opr,SP SP2 5 EOR #opr IMM 2 EOR opr DIR 3 EOR opr EXT 4 Exclusive OR EOR opr,X IX2 4 Accumulator A <— (A) Å (M) 0 – – ³ ³ – EOR opr,X IX1 3 and Memory EOR ,X IX 2 EOR opr,SP SP1 4 EOR opr,SP SP2 5

  21. Bit Manipulation Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles BIT #opr IMM 2 BIT opr DIR 3 BIT opr EXT 4 Bit test (AND) BIT opr,X IX2 4 Accumulator A  (M) 0 – – ³ ³ – BIT opr,X IX1 3 with Memory BIT ,X IX 2 BIT opr,SP SP1 4 BIT opr,SP SP2 5 Clear bit n in BCLR n,opr Mn <— 0 – – – – – – DIR 4 Memory Set bit n in BSET n,opr Mn <— 1 – – – – – – DIR 4 Memory CLC Clear Carry Bit C <— 0 – – – – – 0 INH 1 SEC Set Carry Bit C <— 1 – – – – – 1 INH 1 CLI Clear Interrupt Mask I <— 0 – – 0 – – – INH 2 SEI Set Interrupt Mask I <— 1 – – 1 – – – INH 2

  22. C 0 b7 b0 C b7 b0 C 0 b7 b0 0 C b7 b0 Data Manipulation- Shifts - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles ASL opr DIR 4 ASLA INH 1 Arithmetic ASLX INH 1 Shift Left ³ – – ³ ³ ³ ASL opr,X IX1 4 (Same as LSL) ASL ,X IX 3 ASL opr,SP SP1 5 ASR opr DIR 4 ASRA INH 1 ASRX Arithmetic INH 1 ³ – – ³ ³ ³ ASR opr,X Shift Right IX1 4 ASR ,X IX 3 ASR opr,SP SP1 5 LSL opr DIR 4 LSLA INH 1 LSLX INH 1 Logical Shift Left ³ – – ³ ³ ³ LSL opr,X IX1 4 LSL ,X IX 3 LSL opr,SP SP1 5 LSR opr DIR 4 LSRA INH 1 LSRX INH 1 Logical Shift Right ³ – – 0 ³ ³ LSR opr,X IX1 4 LSR ,X IX 3 LSR opr,SP SP1 5

  23. C b7 b0 C b7 b0 Data Manipulation- Rotates - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles ROL opr DIR 4 ROLA INH 1 ROLX Rotate Left INH 1 ³ – – ³ ³ ³ ROL opr,X through Carry IX1 4 ROL ,X IX 3 ROL opr,SP SP1 5 ROR opr DIR 4 RORA INH 1 RORX Rotate Right INH 1 ³ – – ³ ³ ³ ROR opr,X through Carry IX1 4 ROR ,X IX 3 ROR opr,SP SP1 5

  24. Program Control- Branches - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles Branch if condition is true ( CC, CS, HCC, HCS, Bcc rel PC <— (PC) + $0002 + rel ? cc – – – – – – REL 3 HI, HS, LO, LS, PL, MI, EQ, NE, GE, GT, LE, LT, IH, IL, MC, MS ) BRA rel Branch Always PC <— (PC) + $0002 + rel – – – – – – REL 3 BRN rel Branch Never PC <— (PC) + $0002 – – – – – – REL 3 Branch if Bit n in PC <— (PC) + $0003 + rel DIR/ BRCLR n,opr,rel – – – – – ³ 5 Memory is Clear ? Mn = 0 REL Branch if Bit n in PC <— (PC) + $0003 + rel DIR/ BRSET n,opr,rel – – – – – ³ 5 Memory is Set ? Mn = 1 REL

  25. Find Maximum Value Exercise Write a routine that finds the maximum value in a list of ten data bytes. The list of data bytes starts at address $130. Write your program here:Suggested program steps: ORG $130 Originate data at address $130 DATA FCB $C0,$40,$8B Form table of data bytes FCB $75,$A0,$60 FCB $DB,$25,$B0 FCB $50 ORG $6E00 Originate program at address $6E00 1. Load the number of bytes in the X register. GETBYTE 2. Load accumulator with byte from source address. DECCNT 3. Decrement the X register. 4. If pointer = 0, goto step 8 (DONE) 5. Compare accumulator value against byte pointed to by source pointer. 6. If accumulator value = byte value pointed to by source pointer goto step 3, else step 7. 7. Goto step 2. DONE 8. Done, stay here. HC08-FINDMAXVALExer

  26. Program Control- Special Branching - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles CBEQ opr,rel PC <— (PC) + $0003 +rel DIR 5 ? (A) – (M) = $00 CBEQA #opr,rel PC <— (PC) + $0003 +rel IMM 4 ? (A) – (M) = $00 CBEQX #opr,rel PC <— (PC) + $0003 +rel IMM 4 ? (X) – (M) = $00 Compare and – – – – – – CBEQ X+,rel PC <— (PC) + $0003 +rel IX+ 4 Branch if Equal ? (A) – (M) = $00 CBEQ opr,X+,rel PC <— (PC) + $0002 +rel IX1+ 5 ? (A) – (M) = $00 CBEQ opr,SP,rel PC <— (PC) + $0004 +rel SP1 6 ? (A) – (M) = $00 DBNZ opr,rel M <— (M) – $01 DIR 5 PC <— (PC) + $0003 + rel ? (M) ° 0 DBNZA rel A <— (A) – $01 INH 3 PC <— (PC) + $0002 + rel ? (A) ° 0 DBNZX rel X <— (X) – $01 INH 3 Decrement and PC <— (PC) + $0002 + rel ? (X) ° 0 Branch if not – – – – – – DBNZ X,rel M <— (M) – $01 IX 4 Zero PC <— (PC) + $0002 + rel ? (M) ° 0 DBNZ opr,X,rel M <— (M) – $01 IX1 5 PC <— (PC) + $0003 + rel ? (M) ° 0 DBNZ opr,SP,rel M <— (M) – $01 SP1 6 PC <— (PC) + $0004 + rel ? (M) ° 0

  27. CBEQ and DBNZ • CBEQ combines the CMP and BEQ instruction • Faster table lookup/search operations • DBNZ combines the DEC and BNE instructions • Faster more efficient looping

  28. CBEQ Example * Subroutine that searches a string for the next blank character * and then points the H:X register to the character immediately * following the blank. * H:X is assumed to already point to a location in the string. ORG $00A0 String RMB 50 ;The character string ORG $6E00 Search LDA #$20 ;Load search character Loop CBEQ X+,Out ;Match? BRA Loop ;No match, do it again. * X post increment will occur regardless of whether the branch is * taken. Therefore when a match is found H:X already points to the * next character. Out RTS How could you change this example to avoid searching past the end of the string?

  29. DBNZ Example * Time delay routine * Delay = N x (160.0+0.375) µs for an 8 MHz CPU clock * For example, for delay = 10ms N = 63 N EQU 63 ;Loop counter for 10 ms delay ORG $50 Count RMB 1 ;Loop counter ORG $6E00 Delay LDA #N ;Set delay constant Loop DBNZ Count,Loop ;Inner loop, Count starts at $00 DBNZA Loop RTS How were the values 160.0 and 0.375 derived?

  30. Program Control- Jumps and Subroutines - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles JMP opr DIR 2 JMP opr EXT 3 JMP opr,X Jump to location PC <— Jump Address – – – – – – IX2 4 JMP opr,X IX1 3 JMP ,X IX 2 JSR opr DIR 4 PC <— (PC) + n ( n=1, 2 or 3 ) JSR opr EXT 5 Push (PCL); SP <— (SP) – 1 JSR opr,X Jump to subroutine – – – – – – IX2 6 Push (PCH); SP <— (SP) – 1 JSR opr,X IX1 5 PC <— Unconditional Address JSR ,X IX 4 PC <— (PC) + 2 Branch to Push (PCL); SP <— (SP) – 1 BSR rel – – – – – – REL 4 subroutine Push (PCH); SP <— (SP) – 1 PC <— (PC) + rel Return from SP <— (SP) + 1; Pull (PCH) RTS – – – – – – INH 4 subroutine SP <— (SP) + 1; Pull (PCL)

  31. Program Control- Interrupt - Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles PC <— (PC) + 1 Push (PCL); SP <— (SP) – 1 Push (PCH); SP <— (SP) – 1 Push (X); SP <— (SP) – 1 Push (A); SP <— (SP) – 1 SWI Software Interrupt Push (CCR); SP <— (SP) – 1 – – 1 – – – INH 9 I <— 1 PCH <— Interrupt Vector High Byte PCL <— Interrupt Vector Low Byte SP <— (SP) + 1; Pull (CCR) SP <— (SP) + 1; Pull (A) Return from RTI SP <— (SP) + 1; Pull (X) ³ ³ ³ ³ ³ ³ INH 7 Interrupt SP <— (SP) + 1; Pull (PCH) SP <— (SP) + 1; Pull (PCL)

  32. Binary Coded Decimal Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles Decimal Adjust (A) DAA U – – ³ ³ ³ INH 2 10 Accumulator Nibble Swap NSA contents of A <— (A[3:0]:A[7:4]) – – – – – – INH 3 Accumulator

  33. Special Instructions Source Effect on CCR Address Bus Forms Description Operation V H I N Z C Modes Cycles RSP Reset Stack Pointer SPL <— $FF – – – – – – INH 1 • WAIT: • CPU08 stops processing instructions • waits for an interrupt • STOP: • CPU08 stops processing instructions • Stops the oscillator circuit • Puts MPU in low power state • Waits for interrupt NOP No Operation None – – – – – – INH 1 Stop Processor and I <— 0 STOP – – 0 – – – INH 1 wait for interrupt Stop Oscillator Halt Processor and WAIT I <— 0 – – 0 – – – INH 1 wait for interrupt

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