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Presenter: Shao - Chieh Hou

The Software/Hardware Co-Debug Environment with Emulator Baodong Yu, Xuecheng Zou Department of Electronic Science and Technology Huazhong University of Science and Technology. Presenter: Shao - Chieh Hou. International Database Engineering & Application Symposium (IDEAS’05). Abstact.

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Presenter: Shao - Chieh Hou

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  1. The Software/Hardware Co-Debug Environment with EmulatorBaodong Yu, XuechengZouDepartment of Electronic Science and TechnologyHuazhong University of Science and Technology Presenter: Shao-ChiehHou International Database Engineering & Application Symposium (IDEAS’05)

  2. Abstact • It is a challenge to debug the software and hardware in the SOC for that neither the software nor the hardware is error-free. By combining the emulator and the simulator, with the new software debug engine, the new bus status monitor, and the new checkpoint technology, the high speed, easy-used software/hardware co-debugging environment is presented in this paper.

  3. What’s the problem? • The SoC Design become complex • Consists • Microprocessor • Memory • Another IP • Software • Time-to-market • Integrate both software and hardware as soon as possible • In this way, the SW/HW co-debug environment is needed

  4. Related Works JHDL debugger environment[1]-[3] JTAG use in debug[4]-[6] Processor-base debug and bus monitor[5] Snapshot technology use in hardware debug[8][9] Data output HDL select Internal data get Hardware Software debug with JTAG[6] SW debug engine[7] Software This paper

  5. Software debug engine • Goal: signal step, breakpoint, register modify => Data output /command input => Run-Length encoder => Command decoder JTAG:30MHZ Bandwidth:2.0875MB/s => Achieve the goal => Register modify and monitor

  6. Bus Status Monitor • Goal: monitor the bus status (both system bus and memory bus), and save data into a block-RAM => Compress the bus status => Bus status collect => Data output /command input => Control memory access

  7. Infrastructure for HW debug • Goal: monitor other IP and signal in SoC Scan cell for signal trace Signal capture and compress Embedded logic analyzer control Scan cell control

  8. Result and Conclusion • Software: • Read register • Breakpoint • Step run • Hardware: • Bus monitor • Scan chain • 32-bit REX CPU(100MIPS) Co-debug by match both HW signal and SW values

  9. My Commend • The paper give a good idea for “what the co-debug need both in SW and HW” • The paper idea is similar to our co-debug environment • The paper is lack of experimental result and detailed, but the main idea is useful in SW/HW co-debug.

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