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Hardware/Software Codesign Formal Verification Techniques. ChungYang (Ric) Huang 黃鐘揚 http://cc.ee.ntu.edu.tw/~ric April 20, 2004. Gate. GDSII. RTL. Design Creation. Design Implementation. Physical Implementation. Functional Specification. Design Flow. RTL. Gate. GDSII.
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ChungYang (Ric) Huang 黃鐘揚
http://cc.ee.ntu.edu.tw/~ric
April 20, 2004
GDSII
RTL
Design
Creation
Design
Implementation
Physical
Implementation
Functional
Specification
Design Flow
RTL
Gate
GDSII
What is Design Verification?To verify the correctness of your design
(Find as many design bugs as possible)
Timing diagrams, system or behaviorlevel
descriptions
GDSII
RTL
Design
Creation
Design
Implementation
Physical
Implementation
Functional
Specification
Design Flow
RTL
Gate
GDSII
What is Design Verification?To verify the correctness of your design
(Find as many design bugs as possible)
Specification
Design
Creation
Design
Implementation
Chip Manufacture
Verification vs. TestingHighlevel spec
RTL design
Synthesis/P&R
ICs
Testing
Verification
diff ?
Verify by Simulation1
0
0
0
1
1
1
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
Circuit
01100011
11000011
11000011
01100011
expected
result
“My biggest problem about design verification is that the time is never enough. I can only do my best to run more simulation, but I don’t know whether it is sufficient.”
 Broadcom designer (similar comments from many others)
“It is very hard to write the testbenches and assertions for the design, since I am not a designer. Ask the designer to do it more? No way!!”
 Sun Microsystems verification engineer (similar comments from many others)
Verfication usually takes up to 70% of resource during the design flow
Question: is there “100%” verification?
Try: Run the simulation for a very long time
More about “100%” verification later…
in 2 minutes
What is a property?
P
P
P
P
P
0
0
Observability Problemassert always (count < 16);
P
P
P
P
P
P
P
0
assertion
Output
1
1
0
The difference between
hardware and software simulations
Do I write enough assertions? (Forget it!!)
What if there is a bug in spec?
(Who knows)
Write assertions to facilitate bug hunting
 Conexant design engineer
module assert_always (clk, reset_n, test_expr);
input clk, reset_n, test_expr;
always @(posedge clk) begin
if (reset_n != 1'b0) begin
if (test_expr != 1'b1) begin
ovl_error("");
end
end
end
endmodule
(clk, reset_n,(short_timer_v < long_timer_v));
(http://www.verificationlib.org/)
A constraint satisfaction problem
OUTPUTS
Combinational
Logic
Sequential vs. Combinational PropertiesProperty
Let’s focus on
combinational property first
(i.e. logic functions only, no temporal relationship)
substitute variables with input constraints

0 0 0 0 0
0 0 0 1 1
………
1 1 1 0 1
1 1 1 1 0
represent truth table?
a = 1
c
c
c
c
input variables
a = 0
function = 1
function = 0
Binary Decision Treef
a
b
b
1
0
0
1
1
0
0
1
Set of inputs is called “support”
= (x * fx + x * fx) *
(x * gx + x * gx)
= x * (fx * gx) + x * (fx * gx)
= x * (fx + gx) + x * (fx + gx)
fx
_

x
fx
_
_
_
_
_
_
_
_
_
0
1
_
_
1
0
b
a
a
a
1
0
f = b
b
b
b
c
c
c
c
0
0
1
1
1
1
0
0
1
0
f = a && b
f = a && c
Basic BDD Operationsf = c
OR
OR
f = a&& (b  c)
f = (a && b)  (a && c)
f = b  c
will result in same BDD
independent of building orders
f
counterexample
1
Tautology; f is always = 1
Property is always true
1
0
To prove combinational property by BDDs Build BDDs for f
Any problem ??
The problem?
while we only need one…
b
c
Consider…. Until find one path that evaluates “f = 0”
What’s the difference from simulation??
Binary decision tree
a counterexample is found (END)
0
0
1
0
circuit
1 1
…
…
…
a
b
c
Apply value on target f 0
1 1 1
0
circuit
…
…
…
a
b
c
Make decision on internal nodes 0
Modeling
Engines
GUI
Constraint Solvers in EDA ToolsGDSII
RTL
Design
Creation
Design
Implementation
Physical
Implementation
Functional
Specification
Design Flow
RTL
Gate
GDSII
(Formal) Verification ApplicationsEquivalence Checking
Property Checking
equivalent?
== ?
INPUTS
Equivalence Checking (EC)Golden circuit
INPUTS
OUTPUTS
Combinational
Logic
OUTPUTS
Combinational
Logic
Revised circuit
Starting from the same state in both circuits,
input sequences
Outputs of golden and revised circuits are always the same
What about the register values (states)?
Complexity?
Goto EC fig
REGs
Equivalence CheckingGolden circuit
INPUTS
OUTPUTS
Combinational
Logic
Always
equivalent?
== ?
REGs
OUTPUTS
Combinational
Logic
Always
equivalent?
== ?
Revised circuit
Goto EC fig
GDSII
RTL
Design
Creation
Design
Implementation
Physical
Implementation
Functional
Specification
Design Flow
RTL
Gate
GDSII
Formal Verification ApplicationsEquivalence Checking
Property Checking
Properties (Formal/Temporal functions)
Do I write enough properties? (Forget it!!)
What if there is a bug in spec?
(Who knows)
Write properties to facilitate bug hunting
(No, most properties are sequential)
(No. Equivalence to what?)
“Where am I going to find time to write assertions? I don’t even have time to write comments!”
 Conexant design engineer
“Designers are too busy and lazy to learn new assertion languages and write assertions”
 Verplex market validation
Close to “pushbutton” solution
Semiformal  combines the advantages of both
Simulation trace
Apply formal techniques (state space exploration)
around the simulation state