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Abstract CPU Modeling and Refinement in Metropolis

Abstract CPU Modeling and Refinement in Metropolis. Haibo Zeng, Qi Zhu CS252 Course Project Mentor: Trevor Meyerowitz. Outline. Overview Metropolis Our model Advantages Correctness Limitations Summary. etropolis. Goal. Our CPU Modeling.

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Abstract CPU Modeling and Refinement in Metropolis

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  1. Abstract CPU Modeling and Refinement in Metropolis Haibo Zeng, Qi Zhu CS252 Course Project Mentor: Trevor Meyerowitz

  2. Outline • Overview • Metropolis • Our model • Advantages • Correctness • Limitations • Summary

  3. etropolis Goal Our CPU Modeling Proof of the Design Methodology based on Metropolis How Correctness Advantages Mainly cycle time now; more quantities can be added • Formal • Flexible • Parameterizable Base Construct models by using formal semantics; Easy refinement and Modification; Easily change many Parameters of the CPU models; Formal Semantics Compare Estimation of cycle time SimpleScalar Can be a simulator; but not only a simulator

  4. Metropolis Our work • Arch. library blocks • Parameterizable • Extendable Prove this design methodology Architecture Platform Function Specification Provide blocks • Metropolis Infrastructure • Formal Semantics • Meta model of comp. Design Constraints Abstract description of ISA functionality Can be a simulator Analysis Verification Synthesis Refinement

  5. … RS RS RS FU FU … FU Our model Branch Predictor CDB Controller RS Info. Fetch Process Exec. Process Result Channels Execution Trace … One inst. in a single issue arch.; a group of inst.s in a multi-issue arch. Issue Channel Out of Order Execution Model (Two Processes)

  6. Our model (cont) • Fetch Process: 1. Handles the fetched instructions from execution trace; and issues them to the Exec. Process (single issue or multiple issue). 2. Can integrate branch predictors (so far, we have a 2-bits predictor). • Exec. Process: 1. Handles the operand dependencies, execution and commit. 2. First add inst. to RS (reservation stations), then execute the inst., finally write back the inst. 3. Can add CDB controller (we use buffers to store the inst.s which have been executed already but not committed).

  7. Advantages • Formal Semantics • Based on a formal semantics provided by Metropolis. • Enables a clear design flow. • And the model is easy to be implemented in hardware. • Easy refinement and modification • Modular • Built-in notion of refinement in Metropolis

  8. Advantages (cont) • Parameterizable • Since the model is at a high level, there are many parameters can be configured. • e.g. issue width; branch model; number of FUs; misprediction penalty; instruction types, instruction execution time; reservation station size … • Unified Framework in Metropolis • Can be integrated with other formal models in Metropolis.

  9. Correctness • Compare with SimpleScalar --- Cycle time • Microarchitecure: Intel Xscale Benchmark: MiBench Version 1.0 http://www.eecs.umich.edu/mibench/

  10. Limitations • For the design methodology, more formal usually means the loss of some performance • For our models, some blocks need to be added to make the models more general

  11. Summary • Abstract CPU modeling in Metropolis; Prove the feasibility of constructing CPU model by this formal methodology • Provide several CPU models with different constraints; also provide some library blocks which can be used to construct new models • These abstract models can be configured to simulate different architectures

  12. Future work • Model the memory system • Model interrupts • More branch prediction schemes • Combine it with other Metropolis architecture models • Try more applications

  13. Thanks!

  14. Extra --- Parameterizable • Different Issue Width Benchmark: MiBench Version 1.0 http://www.eecs.umich.edu/mibench/

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