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Computer Organization

Computer Organization. Sequential Logic and Memory Elements. Sequential Logic. Individual logic functions are decision-making functions Combining these functions let us do more complex tasks Sequential logic has time as an important factor Not just in the sense of propagation delay.

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Computer Organization

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  1. Computer Organization Sequential Logic and Memory Elements

  2. Sequential Logic • Individual logic functions are decision-making functions • Combining these functions let us do more complex tasks • Sequential logic has time as an important factor • Not just in the sense of propagation delay

  3. Sequential Logic • Feedback: outputs are fed back into the inputs • Change in input causes a change in an output • This change is fed back as an input • This can cause another output change • Etc. • Problematic keeping track of time sequences of all the changes • Clocked sequential systems

  4. RS Latch • To create a 1-bit memory, we need a circuit to “remember” previous input values • Let output at time t+1 = output at time t regardless of the input values • The Reset-Set latch • bistable (2 valid states) • 2 inputs (Reset and Set) • 2 outputs (Q and Q)

  5. RS Latch Truth Table S Q R Q R S Q Q 0 0 no change 0 1 1 0 1 0 0 1 1 1 invalid RS Latch • S=HI, R=LO sets Q to HI • S=LO, R=HI resets Q to LO • S=LO, R=LO: Q remembers what it was previously

  6. RS Latch • RS Latch can be constructed with NOR gates

  7. RS Latch • Logic Works Simulation

  8. RS Latch with Enable The Enable allows the latch to operate when it is HIGH but when it is LOW prevents the latch from operating.

  9. RS Latch with Preset and Clear Preset and Clear override other inputs (See simulation)

  10. D Latch / D Flip Flop • A Latch is a level-triggered device • the latch will respond when the correct level is attached to the ENABLE input. • A flip flop is an edge-triggered device • Output responds to the input only at the transition between levels of the enabling signal • Leading edge (from LO to HI) • Trailing edge (from HI to LO)

  11. D Latch / D Flip Flop • D latch and D flip flop have only one input (D) and an enabling device (usually a clock) D Latch / Flip Flop Truth Table Enable D Q Q 0 0 no change 0 1 no change 1 0 0 1 1 1 1 0

  12. D Latch • RS Latch with a single input RS Latch D can be latched into Q then enable removed. Then D is free to assume a new value

  13. JK Flip Flop • It is often necessary to sample data at a certain point in time or at a regular interval. • This can be accomplished through edge triggering. • The JK Flip-Flop uses edge triggering to determine when the input information should be passed to the output.

  14. JK Flip Flop • The RS Latch has the pesky situation where RS = 11 is not allowed • Consider the following: S = JQ R = KQ Q = QK + Q Q = JQ + Q

  15. J K Qn+1 0 0 Qn 0 1 0 1 0 1 1 1 Qn JK Flip Flop • See simulation (JKFF.cct)

  16. JK Flip Flop • A single change in an input could trigger a sequence of changes in flip-flop states • Analysis is very complex • It is difficult to keep track of what happens when • Tolerances of timing in gates • inconsistent timing

  17. JK Flip Flop • Add a clock input to enable the inputs (JKFFE.cct) • Doesn’t quite work: output could mess up the inputs • If the clock input is short enough, there should be only one change in the flip-flop states • If the clock stays at 1 too long, you could get continuous flip-flop

  18. Master-Slave JK Flip Flop • Have a master JK FF enabled by some clock pulse CP • Have a slave JK FF enabled by CP • When clock input is 0, master will not change state • When clock input is 1, slave will not change state • See sample (MSJKFF.cct)

  19. JK Flip Flop with Preset and Clear • Asynch portion • Synch portion • See JKFFPC.cct

  20. T Flip-Flop • Connect a single input to both J and K inputs on a JK flip flop T Q(n+1) 0 Q(n) 1 Q(n)

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