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This course outline covers essential topics in testing digital circuits, focusing on defects and fault models relevant for both combinational and sequential circuits. Key techniques such as Automatic Test Pattern Generation (ATPG) are explored with an emphasis on the stuck-at fault model, which identifies various occurrence faults like bridging and transition faults. The course highlights methods for efficient fault detection, including exhaustive algorithms and random pattern generation, along with essential concepts such as controllability and observability.
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ECE260B – CSE241AWinter 2005Testing Website: http://vlsicad.ucsd.edu/courses/ece260b-w05
Outline • Defects and Faults • ATPG for Combinational Circuits • ATPG for Sequential Circuits
Fault Models • Most Popular - “Stuck - at” model Covers many other occurring faults, such as opens and shorts. • a, g : x1 sa1 • b : x1 sa0 or • x2 sa0
Fault Models a • To detect an and-bridging • Detect a s-a-0 and b = 0 • Detect b s-a-0 and a = 0 • To detect a transition fault • Pattern 1: c = 1 • Pattern 2: detect c s-a-1 and b c good 1 bad
Problem with stuck-at model: CMOS open fault Sequential effect Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive!
Problem with stuck-at model: CMOS short fault Causes short circuit between Vdd and GND for A=C=0, B=1 Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration
Exhaustive Algorithm • For n-input circuit, generate all 2n input patterns • Infeasible, unless circuit is partitioned into cones of logic, with < 15 inputs • Perform exhaustive ATPG for each cone • Misses faults that require specific activation patterns for multiple cones to be tested
Random Pattern Generation • Flow chart for method • Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest
Boolean Difference Symbolic Method (Sellers et al.) g = G (X1, X2, …, Xn) for the fault site fj = Fj (g, X1, X2, …, Xn) 1 jm Xi = 0 or 1 for 1 in
Boolean Difference (Sellers, Hsiao, Bearnson) • Shannon’s Expansion Theorem: F (X1, X2, …, Xn) = X2F (X1, 1, …, Xn) + X2F (X1, 0, …, Xn) • Boolean Difference (partial derivative): Fj g • Fault Detection Requirements (for g s-a-0): G (X1, X2, …, Xn) = 1 Fj g = Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) = Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) = 1
Basic Terms, Path Sensitization • Controllability: the ease of controlling the state of a node in the circuit • Observability: the ease of observing the state of a node in the circuit Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) sa0 1 Fault enabling 1 1 1 1 1 0 Fault propagation 0 Techniques Used: D-algorithm, Podem
5-Value Logic • 0 – binary 0 in both good and fault circuit • 1- binary 1 in both good and fault circuit • X – don’t care • D – binary 1 in good circuit, 0 in bad circuit • D – binary 0 in good circuit, 1 in bad circuit
Primitive D-Cube of Failure • Models circuit faults: • Stuck-at-0 • Stuck-at-1 • Bridging fault (short circuit) • Arbitrary change in logic function • AND Output sa0: “1 1 D” • AND Output sa1: “0 X D ” “X 0 D ” • Wire sa0: “D” • Propagation D-cube – models conditions under which fault effect propagates through gate
Forward Implication • Results in logic gate inputs that are significantly labeled so that output is uniquely determined • AND gate forward implication table:
Backward Implication • Unique determination of all gate inputs when the gate output and some of the inputs are given
Path Sensitization Method Circuit Example • Fault Sensitization • Fault Propagation • Line Justification
Path Sensitization Method Circuit Example • Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 D D D D 1 D 0 1 1
Path Sensitization Method Circuit Example • Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears 1 D D 1 1 D D D 1
Path Sensitization Method Circuit Example • Final try: pathg – i – j – k – L – test found! 0 0 D D 1 D D D 1 1
D-Algorithm – Top Level • Number all circuit lines in increasing level order from PIs to POs; • Select a primitive D-cube of the fault to be the test cube; • D-drive (); • Consistency (); • return ();
D-Algorithm – Propagation • D-frontier: all gates whose output is X, at least one input is D or D • J-frontier: all gates whose output is defined, but is not implied by the input values
Example 7.2: Fault A sa0 • Step 1 – D-Drive – Set A = 1 D 1 D
Step 2 -- Example 7.2 • Step 2 – D-Drive – Set f = 0 0 D D 1 D
Step 3 -- Example 7.2 • Step 3 – D-Drive – Set k = 1 1 D 0 D D 1 D
Step 4 -- Example 7.2 • Step 4 – Consistency – Set g = 1 1 1 D 0 D D 1 D
Step 5 -- Example 7.2 • Step 5 – Consistency – f = 0 Alreadyset 1 1 D 0 D D 1 D
Step 6 -- Example 7.2 • Step 6 – Consistency – Set c = 0, Set e = 0 1 1 0 D 0 0 D D 1 D
D-Chain Dies -- Example 7.2 • Step 7 – Consistency – Set B = 0 • D-Chaindies X 1 1 0 D 0 0 0 D D 1 D • Test cube: A, B, C, D, e, f, g, h, k, L
Example 7.3 – Fault s sa1 • Primitive D-cube of Failure 1 D sa1
Example 7.3 – Step 2 s sa1 • Propagation D-cube for v 1 D 1 sa1 D 0 D
Example 7.3 – Step 2 s sa1 • Forward & Backward Implications 0 1 1 1 D 1 1 sa1 D 0 D
Example 7.3 – Step 3 s sa1 • Propagation D-cube for Z – test found! 0 1 1 1 D 1 1 sa1 D 0 D D 1
PODEM High-Level Flow • Assign binary value to unassigned PI • Determine implications of all PIs • Test Generated? If so, done. • Test possible with more assigned PIs? If maybe, go to Step 1 • Is there untried combination of values on assigned PIs? If not, exit: untestable fault • Set untried combination of values on assigned PIs using objectives and backtrace. Then, go to Step 2
Example 7.3 -- Step 1 s sa1 • Select path s –Y for fault propagation sa1
Example 7.3 -- Step 2 s sa1 • Initial objective: Set r to 1 to sensitize fault 1 sa1
Example 7.3 -- Step 3 s sa1 • Backtrace from r 1 sa1
Example 7.3 -- Step 4 s sa1 • Set A = 0 in implication stack 1 0 sa1
Example 7.3 -- Step 5 s sa1 • Forward implications: d = 0, X = 1 1 1 0 0 sa1
Example 7.3 -- Step 6 s sa1 • Initial objective: set r to 1 1 1 0 0 sa1
Example 7.3 -- Step 7 s sa1 • Backtrace from r again 1 1 0 0 sa1
Example 7.3 -- Step 8 s sa1 • Set B to 1. Implications in stack: A = 0, B = 1 1 1 0 0 1 sa1
Example 7.3 -- Step 9 s sa1 • Forward implications: k = 1, m = 0, r = 1, q = 1, Y = 1, s = D, u = D, v = D, Z = 1 1 1 0 0 0 1 sa1 D 1 1 1 D D 1
Backtrack -- Step 10 s sa1 • X-PATH-CHECK shows paths s – Y and s – u – v – Z blocked (D-frontier disappeared) 1 1 0 0 sa1
Step 11 -- s sa1 • Set B = 0 (alternate assignment) 1 0 0 sa1
Backtrack -- s sa1 • Forward implications: d = 0, X = 1, m = 1, r = 0, s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized 1 0 0 0 1 1 0 sa1 1 0 1 0 1
Step 13 -- s sa1 • Set A = 1 (alternate assignment) 1 1 sa1
Step 14 -- s sa1 • Backtrace from r again 1 1 sa1
Step 15 -- s sa1 • Set B = 0. Implications in stack: A = 1, B = 0 1 1 0 sa1