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Handshake protocols for de-synchronization. I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. Sotiriou. Politecnico di Torino, Italy Universitat Politecnica de Catalunya, Barcelona, Spain Cadence Berkeley Lab, Berkeley, USA ICS-FORTH, Crete, Greece.

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handshake protocols for de synchronization

Handshake protocolsfor de-synchronization

I. Blunno, J. Cortadella, A. Kondratyev,

L. Lavagno, K. Lwin and C. Sotiriou

Politecnico di Torino, Italy

Universitat Politecnica de Catalunya, Barcelona, Spain

Cadence Berkeley Lab, Berkeley, USA

ICS-FORTH, Crete, Greece

asynchronous for dummies

Asynchronousfor dummies

I. Blunno, J. Cortadella, A. Kondratyev,

L. Lavagno, K. Lwin and C. Sotiriou

Politecnico di Torino, Italy

Universitat Politecnica de Catalunya, Barcelona, Spain

Cadence Berkeley Lab, Berkeley, USA

ICS-FORTH, Crete, Greece

outline
Outline
  • What is de-synchronization ?
  • Behavioral equivalence
  • 4-phase protocols for de-synchronization
  • Concurrency
  • Correctness
  • An example
slide4

De-synchronize

Asynchronous

CLK

Synchronous

CLK

de synchronization

C

C

C

C

C

C

De-synchronization

L

L

L

L

0

1

0

1

0

0

L

L

de synchronization1
De-synchronization

Distributed controllers substitute the clock network

C

C

C

C

C

C

The data path remains intact !

design flow
Design flow
  • Think synchronous
  • Design synchronous:one clock and edge-triggered flip-flops
  • De-synchronize (automatically)
  • Run it asynchronously
prior work
Prior work
  • Micropipelines (Sutherland, 1989)
  • Local generation of clocks
    • Varshavsky et al., 1995
    • Kol and Ginosar, 1996
  • Theseus Logic (Ligthart et al., 2000)
    • Commercial HDL synthesis tools
    • Direct translation and special registers
  • Phased logic (Linder and Harden, 1996) (Reese, Thornton, Traver, 2003)
    • Conceptually similar
    • Different handshake protocol (2 phase vs. 4 phase)
automatic de synchronization
Automatic de-synchronization
  • Devise an automaticmethod forde-synchronization
  • Identify a subclass of synchronous circuits suitable for de-synchronization
  • Formally prove correctness
outline1
Outline
  • What is de-synchronization ?
  • Behavioral equivalence
  • 4-phase protocols for de-synchronization
  • Concurrency
  • Correctness
  • An example
flow equivalence

Flow equivalence

[Guernic, Talpin, Lann, 2003]

slide39

A

B

flow equivalence1
Flow equivalence

CLK

A 1 3 0 2 1 5 3 1 6 0

B 5 1 2 3 1 4 2 4 3 1

Synchronous behavior

A 1 3 0 2 1 5 3 1 6 0

B 5 1 2 3 1 4 2 4 3 1

De-synchronized behavior

flow equivalence2
Flow equivalence

CLK

A 1 3 0 2 1 5 3 1 6 0

B 5 1 2 3 1 4 2 4 3 1

Synchronous behavior

A 1 3 0 2 1 5 3 1 6 0

B 5 1 2 3 1 4 2 4 3 1

De-synchronized behavior

outline2
Outline
  • What is de-synchronization ?
  • Behavioral equivalence
  • 4-phase protocols for de-synchronization
  • Concurrency
  • Correctness
  • An example
slide43

C

C

C

C

C

C

L

L

L

L

0

1

0

1

0

0

L

L

slide44

C

C

C

C

C

C

slide45

L

C

slide46

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A latch cannot read another data item untilthe successor has captured the current one

A

B

C

D

0

0

0

0

slide47

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A latch cannot read another data item untilthe successor has captured the current one

A

B

C

D

0

1

0

0

slide48

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A latch cannot read another data item untilthe successor has captured the current one

A

B

C

D

0

0

0

0

slide49

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A

B

C

D

1

0

0

0

A latch cannot read another data item untilthe successor has captured the current one

slide50

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A

B

C

D

0

0

0

0

slide51

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A

B

C

D

0

0

0

1

slide52

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A

B

C

D

0

0

0

0

slide53

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A latch cannot become opaque before havingcaptured the data item from its predecessor

A

B

C

D

0

0

1

0

slide54

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A

B

C

D

0

1

1

0

A latch cannot become opaque before havingcaptured the data item from its predecessor

slide55

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A

B

C

D

0

0

1

0

A latch cannot become opaque before havingcaptured the data item from its predecessor

slide56

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A

B

C

D

0

0

0

0

A latch cannot become opaque before havingcaptured the data item from its predecessor

slide57

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A- B+ C- D+

A+ B- C+ D-

A

B

C

D

0

0

0

0

slide58

A

B

A

B

C

D

A+ B+ C+ D+

A- B- C- D-

outline3
Outline
  • What is de-synchronization ?
  • Behavioral equivalence
  • 4-phase protocols for de-synchronization
  • Concurrency
  • Correctness
  • An example
can we increase concurrency

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

Can we increase concurrency ?

not flow-equivalent

slide61

A

data overrun

B

A

A

data lost

B

B

slide62

A+ B+

A- B-

Can we reduce concurrency ? How much ?

slide63

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

(5 states)

A+ B+

A- B-

A+ B+

A- B-

(4 states)

(8 states)

(6 states)

slide64

A

B

A

A

B

B

A

B

A

A

B

B

de-synchronization

model

fully decoupled

(Furber & Day)

GasP, IPCMOS

semi-decoupled

(Furber & Day)

non-overlapping

simple 4-phase

slide65

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

de-synchronization

model

fully decoupled

(Furber & Day)

GasP, IPCMOS

simple 4-phase

non-overlapping

semi-decoupled

(Furber & Day)

slide66

A

B

Rx

Ri

Ro

cntrl

cntrl

Ax

Ai

Ao

Ri+ A- Rx+ B- Ro+

Ai+ Ax+ Ao+

Ri- A+ Rx- B+ Ro-

Ai- Ax- Ao-

(semi-decoupled 4-phase protocol)

slide67

A

B

Rx

Ri

Ro

cntrl

cntrl

Ax

Ai

Ao

A- B-

A+ B+

(semi-decoupled 4-phase protocol)

slide68

A

B

Rx

Ri

Ro

cntrl

cntrl

Ax

Ai

Ao

A- B-

A+ B+

(semi-decoupled 4-phase protocol)

slide69

A

B

Rx

Ri

Ro

cntrl

cntrl

Ax

Ai

Ao

A- B-

A+ B+

(semi-decoupled 4-phase protocol)

slide70

A

B

Rx

Ri

Ro

cntrl

cntrl

Ax

Ai

Ao

A- B-

A+ B+

(semi-decoupled 4-phase protocol)

slide71

A

B

Rx

Ri

Ro

cntrl

cntrl

Ax

Ai

Ao

A- B-

A+ B+

(semi-decoupled 4-phase protocol)

slide72

A

B

Rx

Ri

Ro

cntrl

cntrl

Ax

Ai

Ao

A- B-

A+ B+

(semi-decoupled 4-phase protocol)

slide73

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

outline4
Outline
  • What is de-synchronization ?
  • Behavioral equivalence
  • 4-phase protocols for de-synchronization
  • Concurrency
  • Correctness
  • An example
slide77

A+ B+

A- B-

Theorem: the de-synchronization protocol preserves flow-equivalence

Proof:by induction on the length of the traces

Induction hypothesis: same latch values at reset

Induction step:

same values at cycle i same values at cycle i+1

slide78

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

slide79

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

Theorem: any reduction in concurrency preserves flow-equivalence

slide80

Semi-

decoupled

Fully

decoupled

Semi-

decoupled

Fully

decoupled

Semi-

decoupled

non-

overlapping

non-

overlapping

Any hybrid approach preserves

flow-equivalence !

slide81

A

B

C

D

A+ B+ C+ D+

A- B- C- D-

slide82

A

B

C

D

A+ B+ C+ D+

A- B- C- D-

semi-decoupled

non-overlapping

fullydecoupled

Flow-equivalence is preserved, … but …

liveness
Liveness
  • Preservation of flow-equivalence:all the generated traces are equivalent
  • Are all traces generated ?(Is the marked graph live ?)Not always !
slide84

A+ B+ C+ D+

A- B- C- D-

Semi-decoupled 4-phase handshake protocol

Liveness: all cycles have at least one token [Commoner 1971]

slide85

A+ B+ C+ D+

A- B- C- D-

Simple 4-phase handshake protocol

results about liveness
Results about liveness
  • At least three latches in a ring are required with only one data token circulating[Muller 1962]
  • Theorem (this paper):any hybrid combination of protocols is live if the simple 4-phase protocol is not usedProof: any cycle has at least one token
slide87

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

Valid for

de-synchronization

de-synchronization

model

fully decoupled

(Furber & Day)

GasP, IPCMOS

simple 4-phase

non-overlapping

semi-decoupled

(Furber & Day)

outline5
Outline
  • What is de-synchronization ?
  • Behavioral equivalence
  • 4-phase protocols for de-synchronization
  • Concurrency
  • Correctness
  • An example
slide91

Synchronous RTL

Synchronous

Desynchronized

=

Cycle: 4.4ns

Power: 70.9mW

Area: 372,656m

Cycle: 4.45ns

Power: 71.2mW

Area: 378,058m

  • All numbers are after Placement & Routing
  • Total of 1500 flip-flops, 3000 latches
  • DE-SYNC design includes 5 controllers, each driving 2 clock trees
  • Power numbers include the clock tree
  • Technology: UCM/Virtual Silicon 0.18 µm
de synchronized dlx on fpga
De-synchronized DLX on FPGA

(demo outside the conference room)

discussion
Discussion
  • The de-synchronization model provides an abstraction of the timing behavior
slide94

[5,7]

[0,0]

[3,5]

A

B

E

[3,5]

[2,3]

[5,7]

D

[2,3]

[3,5]

[8,9]

F

[2,4]

C

[1,2]

[1,2]

[2,3]

G

[2,4]

[1,2]

[8,9]

  • Timing analysis
  • Exploration of the design space
slide95

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

A+ B+

A- B-

de-synchronization

model

fully decoupled

(Furber & Day)

GasP, IPCMOS

simple 4-phase

non-overlapping

semi-decoupled

(Furber & Day)

conclusions
Conclusions
  • EDA tools require a formal support(they must work for all circuits)
  • A complete characterization of 4-phase protocols has been presented(partial order based on concurrency)
  • Design flow developed at Cadence Berkeley Labs
    • Automated from gate netlist
    • Static timing analysis to derive matched delays
    • Constrained P&R to meet timing constraints