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Rich Katz, Grunt Engineer NASA Office of Logic Design

Workshop: EEPROM Reliability Welcome, Introduction and Overview; The Ideal Device. Rich Katz, Grunt Engineer NASA Office of Logic Design. Schedule and Logistics. 9:30 am Meeting starts 12:30 pm Lunch. Buildings 1 and 21 have cafeterias 1:45 pm Meeting resumes

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Rich Katz, Grunt Engineer NASA Office of Logic Design

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  1. Workshop: EEPROM ReliabilityWelcome, Introduction and Overview; The Ideal Device Rich Katz, Grunt Engineer NASA Office of Logic Design

  2. Schedule and Logistics • 9:30 am Meeting starts • 12:30 pm Lunch. Buildings 1 and 21 have cafeterias • 1:45 pm Meeting resumes • 5:00 pm Meeting concludes (planned) Audio and video recording is not permitted.

  3. Presenters • Richard Katz, NASA Office of Logic Design: Welcome, Introduction and Overview; The Ideal Device • Michael Sampson, NASA GSFC Office of Systems Safety and Mission Assurance: Opening Remarks • Rod Barto, NASA Office of Logic Design: Circuit Issues for Hitachi-die EEPROMs • Jean BERTRAND – CNES, QA Engineer in Charge of VLSI: Failure of an HN58C1001 based EEPROM • Erik Jerkersson, Saab Ericsson Space AB: The EEPROM Experience • Amy J. Hurley, Naval Research Labs: SECCHI EEPROM Issues & Resolutions • Greg Clifford, Silver Engineering, Inc.: One EEPROM Page Anomaly Study • Ken Li, NASA Goddard Space Flight Center: ST-5 Experiences • Yuan Chen: JPL: EEPROM Application Review and Recommendations • Jose Florez, NASA Goddard Space Flight Center: NASA Advisory NA-GSFC-2005-04; Application of Hitachi 1-Mbit Die Based EEPROM Technology to Space Applications • Mike Fitzpatrick and Dennis Adams, Northrop-Grumman: CMOS / SONOS EEPROM Reliability Overview • Austin Semiconductor, Jeff Kendziorski: Reliability, Application Use, Unique Test Screening & Concepts/Ideas • Maxwell Technologies: Larry L. Longden and Ed Patnaude

  4. Proprietary Information • Memory vendors may wish to present proprietary information on their slides. • Competing vendors may be asked to “step outside” for this portion of the presentation.

  5. Some Idealized Memory Specs Capacity: >= 1 megabit Speed: not critical Cycles: >= 10^4 Storage Time: >= 50 years Safety: * externally supplied signals (clock, high voltage) must be present to alter any memory contents * JEDEC compatible software write protection discrete WRITE_DISABLE* line EDAC: SEC/DED with fault signal available Verification: test mode where instead of a data value is digitized number is output which is a measure of the charge on a cell. this will permit trending.

  6. Some Idealized Memory Specs SEU's: Peripheral registers must be SEU hardened. That is, address holding registers, data latches, etc. Total Dose: Goal: >= 100 krad(Si). Hard Requirement: >= 30 krad(Si) SEL: Immune SED: Single event damage. Many current devices can be fatally damaged (rupture) when writing due to a single heavy ion. During writes high voltage is on.

  7. Some Idealized Memory Specs FSM Design: * No lockup states and no modes where a part can be damaged. * Many NVM devices (e.g., some flash and EEPROM) have controllers that can lock up and require power cycling to regain functionality. I/O: * Looks like 3.3V will be compatible with everything these days. * Make flexible. * Cold-sparing capability a plus. * 5V tolerant inputs a plus. Status: Both "busy" signal and inverted data techniques.

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