DEPFET pixel sensor – concept and status

1. DEPFET pixel sensor – concept and status R.H. Richtera, L. Andriceka, P. Fischerb, M. Harterb, K. Heinzingera, S. Herrmanna, P. Lechnera, R. Kohrsc, H. Krügerc, G. Lutza, M. Porroa, I. Pericc, G. Schallera, M. Schnecke-Radaua, F. Schoppera, H. Soltaua, L. Strüdera, J. Treisa, M. Trimplc, N. Wermesc aMPI Halbleiterlabor Munich bUniv. of Mannheim cUniv. of Bonn • DEP(leted)F(ield)E(ffect)T(ransistor) operation principles • First results of DEPFET prototype run with new technology • Technology parameter • Device parameter • Noise / Amplification • First measurements on clear mechanisms • Status of read out electronics and steering chips • Summary R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

2. DEPFET-Principle of Operation MIP source top gate drain clear bulk n+ p+ p+ n+ n+ p n s i internal gate x a + - - y - - - r t - - e + m - m y s + - n + - p+ rear contact Potential distribution: internal Gate ~1µm Backcontact Drain 50 µm Source [TeSCA-Simulation] FET-Transistor integrated in every pixel (first amplification) Electrons are collected in „internal gate“ and modulate the transistor-current Signal charge removed via clear contact R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

3. DEPFET-Principle of Operation +15V source top gate drain clear bulk 0V 0V n+ p+ p+ n+ n+ p n s i internal gate x a - - y - - - r t - e m m y s - n p+ rear contact Potential distribution: internal Gate ~1µm Backcontact Drain 50 µm Source [TeSCA-Simulation] FET-Transistor integrated in every pixel (first amplification) Electrons are collected in „internal gate“ and modulate the transistor-current Signal charge removed via clear contact R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

4. DEPletedFieldEffectTransistor Module Concept / Pixel Cell sensitive area thinned to 50 mm, supported by a 300 mm thick frame of silicon R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

5. DEPFET Technologyon 6” wafer at MPI–Semiconductor Lab Double poly / double aluminum process on high ohmic n- substrate perpendicular to channel (with clear) along p-channel R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

6. Pixel prototype production (6“ wafer)for XEUS and LC (TESLA) Aim: Select design options for an optimized array operation (no charge loss, high gain, low noise, good clear operation) On base of these results => production of full size sensors Many test arrays - Circular and linear DEPFETS up to 64 x 128 pixels minimum pixel size about 25 x 25 µm² - variety of special test structures R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

7. Technology characterization • Leakage currents of diodes (fully depleted 450µm) • I = 100 – 200pA /cm2 • Depletion voltages (variation in Wacker substrates) • Two groups: Vdepl = 30-40V • = 130V • Oxide characterisation: • Vfb (Polysilicon) ca. -1V (ok) • Interdielectric breakdown voltages: • Poly I (Clear gate) to Si: > 100V • Poly II (DEPFET gate) to Si: > 100V • Metal I to Si > 200V • Poly I to Poly II > 20V R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

8. DEPFET measurements (I)on rectangular test transistors (W = 120µm L = 5µm) => 1/gd ~ 300 kΩ @ 30µA for a matrix pixel device of W/L = 12µm/5µm) R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

9. gm ~ 20 µS @ 30µA (28µS @ 60µA) • (for a matrix pixel device • of W/L = 12µm/5µm) DEPFET measurements (II)on rectangular test transistors (W = 120µm L = 5µm) • VTH ~ 0V • Device can be completely • switched off. • Rectangular transistor concept with lateral polysilicon isolation frames works! (necessary for small pixel sizes) Small gm of external gate is intended for noise reduction. R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

10. SUBTHRESHOLD CHARACTERISTICS MEASUREMENTS R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

11. Potential of the empty Internal Gate L = 4 (3) µm L= 5 (4) µm L = 6 (5) µm L = 7 (6) µm L = 10 (9) µm ToSCA – 2D device simulation R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

12. SPECTROSCOPIC MEASUREMENT WITH SOURCE FOLLOWER noise peak 3.6 el. Circular STD DM CG T=295 K Shaping Time=3ms Total counts: 92850 FWHM (Mn Ka)= 146 eV ENC (n.pk.) = 3.6 R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

13. ENC on Circular STD DM CG Source follower mode at R.T. R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

14. Internal amplification / small arrays • Measured current change per signal electron • (calibration with Fe55) • Circular shape: ca. 300pA/e- • Rectangular shape: ca. 400pA/e- (@40µA) • Measurements on small arrays (4x8 pixel - single metal): • DEPMOS transistors controlable • Current dispersion about 5% • Larger Arrays (128x64 pixel – double metal) • still in production. TeSCA (2D, time dependent) hit response to a generation of 1600 electron-hole pairs R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

15. Potential distribution (3D Poisson equ.) DEPFET - a device without Reset Noise • In principle it is possibleto remove all residual • charge from the internal gate during clear • no reset noise But at which voltage ? What is the effort? – Clocked clear gate? Clear region + internal gate

16. “ Complete Clear“ measurements • DEPFET current immediately • after clear pulse(s) • Saturation of current indicates that • no any further charge is removed • Clear is complete Supported by noise measurements Noise gets at the lowest level at the same voltage where the current start to saturate. R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

17. Status: Switcher II Switcher II: • steering chip for DEPFET matrices • AMS 0.8µm HV • versatile steering sequences • ( flexible pattern) • high speed +high voltage range (20V) • drives 64 DEPFET-rows • (can be daisy chained) • produced 12/2002 4.6 mm 4.8 mm • Results: • power consumption: • ~1mW /channel • tested ok to 30MHz [I.Peric (Bonn) / P.Fischer (Mannheim)] R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

18. Status: CURO II • fast RO chip for DEPFETs • 128 channels „CUrrent ReadOut“ • size: 4.5 x 4.5 mm2 • TSMC 0.25µm, 5metal • costs: 30k$ • submitted: September 2003 • returns: November 2003 4.5mm Design features: • fast current based memory cells • Correlated double sampling within 40ns • (suppresses 1/f noise) • automatic pedestal subtraction • hit identification + zero suppression [M.Trimpl (Bonn)] 4.5mm R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003

19. Summary First DEPFET prototype run using a new DEPFET technology was successfully produced Technology and device parameter were measured – very good results! First Measurements on single and double pixel - electronic noise about 3 electrons at room temperature - complete clear achievable with moderate voltages First arrays with single metal are tested now Chip development: Line control chip Switcher II is ready for use. Readout Chip CURRO II will be back from TSMC this month Larger pixel arrays with double metal technology are in production R. H. Richter et al - ECFA Linear Collider Workshop, Montpellier, 13. - 16. Nov. 2003