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All-digital RF signal generation using ΔΣ modulation for mobile communication terminals

All-digital RF signal generation using ΔΣ modulation for mobile communication terminals. Antoine Frappé antoine.frappe@isen.fr Directeur de Thèse : Andreas Kaiser. Equipe Microélectronique Silicium http://www.isen.fr/~electronique_lille. Outline. Background

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All-digital RF signal generation using ΔΣ modulation for mobile communication terminals

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  1. All-digital RF signal generation using ΔΣ modulation for mobile communication terminals Antoine Frappé antoine.frappe@isen.fr Directeur de Thèse : Andreas Kaiser Equipe Microélectronique Silicium http://www.isen.fr/~electronique_lille

  2. Outline • Background • Digital transmitter architecture • ΔΣ modulator system design • Digital transmitter circuit design • Experimental results • Conclusion and future directions

  3. Outline • Background • Worldwide Communications Systems • Ideal Software Radio • State-of-the-art in digital transmitters • Digital transmitter architecture • ΔΣ modulator system design • Digital transmitter circuit design • Experimental results • Conclusion and future directions

  4. Europe : GSM900 / DCS1800 / UMTS channel Power Fre-quency Standard frequency band United-States : IS-95 / CDMA2000 China : TD-SCDMA Gabon : GSM900 Worldwide Communications Systems Standards diversity • Each area has its own mobile standards • Broadband standards • Wi-Fi, IEEE802.11 • Cordless systems • DECT • Short-range systems • Bluetooth

  5. GSM IS-95 Worldwide Communications Systems Bi-standard or tri-standard mobile phones VOICESMSDATAVIDEO… UMTS Single chip Large area needed and high power consumptionNo reconfigurabilityHigh manufacturing cost Design of a reconfigurable RF transmitter IC able to address every standard

  6. DSP DAC Evolution towards ideal software radio

  7. Early proposed concept • P. Asbeck et al., 2001 • Concept of a digital transmitter based on bandpass ΔΣ modulation and switching PA P. M. Asbeck, L. E. Larson, and I. G. Galton, "Synergistic design of DSP and power amplifiers for wireless communications," IEEE Trans. on Microwave Theory and Techniques, vol. 49, pp. 2163-2169, 2001.

  8. State-of-the-art in digital transmitters • J. Sommarek et al, 2004 • Digital IF implementation (175MHz) • ΔΣ bandwidth is 5MHz (channel width) J. Sommarek, et al., "A digital modulator with bandpass delta-sigma modulator," IEEE ESSCIRC, pp. 159-162, 2004.

  9. Outline • Background • Digital transmitter architecture • Digital transmitter concept • Proposed architecture for UMTS • Architecture choices • ΔΣ modulator system design • Digital transmitter circuit design • Experimental results • Conclusion and future directions

  10. Digital Transmitter Concept VDD = 1V Power-DAC Digital Signal Processing 1 bit • Switching-mode Power Amplifier • Voltage mode  Good efficiency • Implemented with an inverter • Generation of a 1-bit digital RF signal

  11. UMTS standard specifications • WCDMA access mode with Frequency Division Duplex • Emission : 5MHz wide channels at 1.92 – 1.98GHz EVM < 17.5% Typical transmitter ~ 7-8% Must be increased by ~10dB for margin

  12. 5MHz Outside-band Noise-shaping 30MHz 60MHz 30MHz Proposed architecture Fs=3.84MHz LxFs=122.88MHz 2Fc=3.9GHz 4Fc=7.8GHz UMTS: Fc=1.95GHz

  13. Standard band ΔΣ bandwidth power Analog filter frequency response ΔΣ-shaped quantization noise frequency Fixed carrierfrequency Architecture choices (1) Direct upconversion Standard band Two-step upconversion ΔΣ bandwidth power Analog filter frequency response ΔΣ-shaped quantization noise frequency Variable carrierfrequency

  14. Architecture choices (2) EXAMPLE UMTS standard Digital RF mixer • Sampling frequency is equal to 4 x fc • Interleaving operation between I and Q channels • One sample on two is unused on each channel • IF upconversion • 5MHz channel placed in [-30MHz ; 30MHz] • RF upconversion • [-30MHz ; 30MHz ] band placed around 1.95GHz n = 0,4,8,12,…

  15. {1,0,-1,0} I BP ΔΣ Q {1,0,-1,0} n 1 1 1 1 n n n n 1 n n 1 1 I {0,1,0,-1} LP ΔΣ Q {1,0,-1,0} LP ΔΣ I LP ΔΣ {0,1,0,-1} ΔT Q LP ΔΣ {0,1,0,-1} Architecture choices (3) • Bandpass ΔΣ implementation • Lowpass ΔΣ implementation • Equivalent complexity • Digital mixer on 1 bit • LP ΔΣ sampling frequency is twice lower ΔT = 1/4fc

  16. {1,0,-1,0} {1,0,-1,0} 1 1 1 n n 1 1 1 n n I I INT LP ΔΣ LP ΔΣ Q Q LP ΔΣ LP ΔΣ {0,1,0,-1} {0,1,0,-1} ΔT ΔT’ ΔT’ Architectures choices (4) • Synchronized operation • Phase shift issue • Resolved by interpolation on Q channel Digital upconverter output spectrum ΔT’ = 1/2fc

  17. Digital RF transmitter architecture Conclusion • Based on ΔΣ modulation and switching-mode power amplification • ΔΣ modulator architecture for UMTS test case • Bandwidth 100MHz • Sampling frequency 3.9GS/s • Around 70dB of SNDR  12 effective bits • ~25dB of digital gain control

  18. Outline • Background • Digital transmitter architecture • ΔΣ modulator system design • Architecture optimization • Implementation strategies • Digital transmitter circuit design • Experimental results • Conclusion and future directions

  19. ΔΣ modulator system design 16 bits 1 bit • 3rd order lowpass ΔΣ modulator • Major feedback creates a 40MHz notch • OSR=~40 • Bandpass is ~100MHz • Sampling rate is 3.9GS/s

  20. Simulation results SNDR vs Amplitude level Matlab simulation results -3dBFS

  21. Architecture optimization • Power-of-two coefficients • Accumulator  Integrator (minimize longest path) • Signals quantization (VHDL simulations)

  22. Simulation results • ACLR@5MHz = 74.7dB • ACLR@10MHz = 72.2dB

  23. Implementation issues • Sample rate is 3.9GS/s (~250ps period) • Critical path • 4 signals to add • 2 consecutive adders in the signal path • Classical implementation in 2’s complement • Carry propagation  Incompatible with the available period

  24. Implementation strategies Borrow-Save arithmetic LSB MSB EXAMPLE Addition of 2 BS • Advantages: • No carry propagation • Several additions at the same time • Disadvantages: • Twice more bits to implement • Full custom design

  25. FA FA FA FA FA FA Implementation strategies Borrow-Save arithmetic Sample rate  3.9GS/s 250ps period FA FA FA • Borrow-Save arithmetic instead of 2’s-complement •  No carry propagation and constant-time additions • Maximum delay in critical path is 3.δ(FA) • Design of a logic cell with a delay less than 250ps / 3 ~ 80ps - Differential dynamic logic cells controlled by 3-phase clocks (DLL) Logic comparator

  26. Implementation strategies Non-exact quantization New problem: Sign evaluation needs carry propagation Performances remain good with low complexity

  27. FA FA FA FA FA FA FA FA FA Implementation strategies Output Signal Precomputation Sample rate  3.9GS/s 250ps period FA FA FA

  28. ΔΣ modulator system design Conclusion • Implementation of a very high-speed digital ΔΣ modulator with : • redundant arithmetic • non-exact quantization • output signal precomputation • Covered by a patent FR0752701 (US application in progress)

  29. Outline • Background • Digital transmitter architecture • ΔΣ modulator system design • Digital transmitter circuit design • IC block structure and chip overview • ΔΣ core layout • Experimental results • Conclusion and future directions

  30. IC block structure

  31. I inputs VddANA VddCLK VddDS Q inputs Output buffers Multiplexer Clock shaper & DLL ΔΣcore & Sample rate conversion Compensation cell Clock tree (adjusted to equalize the delay) First chip overview in 90nm CMOS 3mm (Without M7) 1mm

  32. Slice ΔΣ core layout • Area : • 350 x 160µm² = 0.056mm² • ~8000 transistors

  33. Full Adder Slice example layout

  34. Dynamic logic style Sum (or carry) calculation block : Sum evaluation Sum dynamic logic Carry evaluation Carry dynamic logic Can be modified to obtain any logic function

  35. Outline • Background • Digital transmitter architecture • ΔΣ modulator system design • Digital transmitter circuit design • Experimental results • First and second chip overview • Test setup • Headlines of measurement results • Comparison with other works • Conclusion and future directions

  36. First chip test & Measurement results • Measurement results on output stages • 2 main issues for core functionality: • Oscillations on power and ground inside the chip • Bad initialization of the delta-sigma core • Corrections are implemented on a second chip in 90nm CMOS

  37. Second chip overview (90nm CMOS)

  38. Test setup 10MHz reference Matlab File with WCDMA signal 7.8GHz frequency synthesizer .m Master clock Bias tee IQ signals @ 121.875MS/s+ data clocks IQ signals @ 243.75MS/s+ data clocks DUT DC block FPGA CycloneII with upconverting & filtering software Balun Spectrum analyzerorDigitizing oscilloscope Arbitrary Waveform Generator (AWG420) or Pattern Generator

  39. Headlines of measurement results • Full functionality up to 4GHz (instead of the expected 8GHz rate) • Standard bands addressed up to 1GHz • Maximum bandwidth is 50MHz (proportional to the sampling rate) RF output spectrum RF output spectrum

  40. SNDR measurement SIMULATIONof the ΔΣ core ~20dB MEASUREMENT Input : sine wave

  41. Digital core functionality Eye diagram at the RF output Jitter = 13.24psRMS MUX 4fc Example of an output spectrum with a DC input and a 2.5GHz clock (single-ended output) Analog output Digital data stream

  42. Measurement results (2.6GHz clock) (1) • UMTS test case (fc=1.95GHz) • Measurements at a 2.6GHz clock frequency • Fundamental band at 650MHz • Image band at 1.95GHz (degraded results) • Relative bandwidth is 30MHz 10.45dB power sinx/x Relative bandwidth f s/4 3fs/4 frequency fs

  43. Measurement results (2.6GHz clock) (2) 5MHz QPSK channel with -3dBFS power 650MHzfundamental band ACPR~52dB 5MHz +10MHz -5MHz +5MHz -10MHz 1.95GHz image band ACPR~44dB +10MHz 5MHz -5MHz +5MHz -10MHz

  44. Measurement results (2.6GHz clock) (3) ACPR ACPR vs amplitude for fundamental and image bands 5MHz QPSK channel with 8.1dB PAPR VHDL SIMULATIONS : ACPR max = 74.7dB

  45. Measurement results (2.6GHz clock) (3) EVM UMTS EVM requirements : <17.5% Typical transmitter EVM : 7~8% 5MHz QPSK channelwith -3dBFS power 650MHz band 1.95GHz band

  46. Power consumption

  47. Summary of measurements

  48. Comparison with other works [1] J. Sommarek, et al., "A digital modulator with bandpass delta-sigma modulator," IEEE ESSCIRC, pp. 159-162, 2004.

  49. Comparison with other works • [2] Digital-to-RF converter (DRFC) • 2nd order MASH ΔΣ modulator providing 3-bit input signals • SNR=30dB over 200MHz • Current-mode output stage • ΔΣ sampling frequency is 2.5GS/s  simple structure [2] A. Jerng and C. G. Sodini, "A Wideband Delta-Sigma Digital-RF Modulator for High Data Rate Transmitters," IEEE J. Solid-State Circuits, vol. 42, pp. 1710-1722, 2007.

  50. Comparison with other works • [3] DRFC with 10-bit 307.2MS/s oversampled input signals • 41/56dB ACPR (for 5MHz channels and 25dBm output power) • EVM<2% over 60dB of control range [3] P. Eloranta, et al., "A WCDMA Transmitter in 0.13µm CMOS Using Direct-Digital RF Modulator," ISSCC Dig. Tech. Papers, pp. 340-341, 2007.

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