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Hall– D Level-1 Trigger Commissioning Part II

Hall– D Level-1 Trigger Commissioning Part II. A.Somov, H.Dong Jefferson Lab 12 GeV Trigger Workshop, July 8, 2010. Play Back Test Vector in Hall-D commissioning Hall-D member commissioning responsibilities Single crate Trigger Test Stand. Test Vector implementation Future plans.

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Hall– D Level-1 Trigger Commissioning Part II

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  1. Hall–D Level-1 Trigger Commissioning Part II A.Somov, H.Dong Jefferson Lab 12 GeV Trigger Workshop, July 8, 2010 • Play Back Test Vector in Hall-D commissioning • Hall-D member commissioning responsibilities • Single crate Trigger Test Stand. Test Vector implementation • Future plans

  2. Play Back Test Vector in Hall-D Commissioning Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 2 • Use Test Vector to check hardware performance: • Load predefined data amplitudes (patterns) corresponding to specific trigger types • (cosmics, physics, …) to FADC250 memory. Verify triggers produced by electronics. • Load signal amplitudes taken from Geant to the FADC250’s and compare the trigger • output with the Level-1 bit-wise simulation. • Test/debug performance of online monitors (scalers).

  3. Hall-D Trigger Commissioning Responsibilities Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 3 Software to be developed by Hall-D members Play Back Test Vector implementation Crate Run Control DB to TS crate ROC FADC 250 Board Control Board Initialization Load FPGA, Load Test Vector samples cMsg Level-1 Trigger Control • • • trigger type & data FADC 250 CODA CODA CTP SD cMsg Lelev-1 Online Monitor Data Quality Monitor TI

  4. Trigger Test Stand ROCK TI FADC Trig OUT Trig IN VME Trig IN Play Back - CODA - Load Samples Discriminator Pulse Generator Trigger Delay Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 4 • Load signal pulse amplitudes (data samples) to the FADC FPGA memory • Use external pulse generator • - for the trigger interrupt (initiate FADC VME readout) • - to send Play Back signal to the FADC through the VME P2 bus. Play Back pulse width defined how • many data samples to process • Readout pulse shapes using CODA • - check FADC readout modes: Window Raw Data (data samples for the trigger window), • Pulse Raw Data (data samples around the ADC threshold) , Pulse Integral (energy sum)

  5. Trigger Test Stand Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 5 Amplitudes loaded to FADC250 FPGA • Different pulse shapes can be loaded to • each of 16 FADC channels • - the memory size of each channel corresponds • to 32 data samples x 4 ns = 128 ns • FADC was operated in the Window Raw • Data mode, i.e., readout out specific number • of data samples • The Play Back pulse width ~130 ns Readout Window Play Back pulse

  6. Summary / Future Plans Hall-D Level-1 Trigger Commissioning, 12 GeV Trigger Workshop at CNU, July 08, 2010 6 • The play back mode has been implemented and tested using the single crate Test Stand • - different signal shapes can be loaded to each FADC channels • Level-1 trigger bit-wise simulation is currently under development • We have started preparing online software for the Level-1 trigger commissioning • We are waiting for more electronics boards and “official” DAQ software for them. The • two crate test stand will hopefully be ready by the end of this year

  7. Test Vector Implementation Hai Dong Ed Jastrzembski David Abbott Ben Rayado Alex Somov Play Back TD TI Trigger FADC • • • 16 ch SD SD • • • 1 - 16 FADC CTP SSP TS GTP • • • 1 - 8 FADC SSP • • • 16 ch • Load FADC amplitudes of signal pulses to FPGA’s memory. • Trigger Supervisor initiates processing of the samples through the trigger hardware. Play Back signal will be delivered to the FADC through one of the trigger lines.

  8. Play Back Mode: FADC pulse in the memory 16 x 4 ns = 64 ns (currently) play back pulse Current version of FADC250 Trig from TI (one line for play back) Load Samples to Memory VMEbus Altera FPGA Play Back FIFO LX25 Self Trigger CTP FX20  LX25 FIFO • Load amplitudes of signal pulses (samples) to FPGA memory. • Play Back pulse width defines how many samples to process. • Trigger from TI initiates the VME readout (trigger can also be initiated by FX20 – self trigger mode)

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