On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming

1. On Logic Synthesisof Conventionally Hard to Synthesize Circuits Using Genetic Programming Petr Fišer, Jan Schmidt Faculty of Information Technology, Czech Technical University in Prague fiserp@fit.cvut.cz, schmidt@fit.cvut.cz Zdeněk Vašíček, Lukáš Sekanina Faculty of Information Technology, Brno University of Technology vasicek@fit.vutbr.cz, sekanina@fit.vutbr.cz

2. Outline • Motivation • Hard to Synthesize Circuits • Cartesian Genetic Programming • Experimental Results • Conclusions DDECS’10

3. Motivation Target: synthesis (minimization) of combinational circuits – multi-level networks Problem: conventional synthesis tools “fail” on some circuits. • Synthesized networks are sometimes orders of magnitude larger the expected size • Synthesis fails even for very small circuits  There is a class of hard to synthesize circuits Genetic programming could help DDECS’10

4. Hard to Synthesize Circuits Several classes of such: • LEKO and LEKU benchmarks • Realistic LEKU benchmarks • Difficult standard benchmark circuits • Parity benchmark circuits • Tautology and near-tautology circuits DDECS’10

5. LEKO and LEKU Benchmarks Logic Examples with Known Optimum (LEKO) Logic Examples with Known Upper Bound (LEKU) • Published inJ. Cong and K. Minkovich, “Optimality study of logic synthesis for LUT-based FPGAs”, IEEE Trans. CAD, vol. 26, pp. 230–239, Feb. 2007 • Originally for testing LUT mappers • Construction: • Small artificial circuit (7 LUTs)is replicated (e.g. 10-times) • The network is collapsed into a two-levelrepresentation • It is mapped into 2-input gates Large circuit is obtained • Both commercial and academic tools produce results 500-times the optimum size!  synthesis fails, because of the circuit is large DDECS’10

6. Realistic LEKU Benchmarks • Cong’s benchmarks are artificial • However, the same benchmark generation process (collapsing & mapping) may be applied to any circuit • For most of real circuits, collapsing&mapping produces large networks as well • … and the consequences are the same:  synthesis fails, because of the circuit is large DDECS’10

7. Difficult Standard Benchmark Circuits • Some circuits from standard banchmark sets (LGSynth, ISCAS, IWLS, MCNC) are hard to synthesize as well • Mostly because XOR decomposition is needed • In most of available synthesis tools it is not supported  synthesis fails, even for small circuits DDECS’10

8. Parity Benchmark Circuits • The above-mentioned problem can be artificially induced for any circuit: • A parity tree is appended to the circuit • The network is collapsed intoa two-level representation • It is mapped into 2-input gates • Sometimes a large circuit is obtained, sometimes not • XOR decomposition capability is necessary to obtain good results  synthesis fails, for both small and big circuits DDECS’10

9. Tautology and Near-Tautology Circuits • Artificially large representations of small circuits: • Random SOP with many terms is generated • This SOP is tautology, or near-tautology (only few minterms missing to tautology) • This SOP is mapped into 2-input gates • The circuit is a constant (or just a few gates). Synthesis tools are not able to discover it, because of the representation is too large  synthesis fails, because of the circuit is large DDECS’10

10. Motivation, cont. Common properties of all these classes: • We know the complexity upper bound, which is rather small • Standard synthesis fails  There is a need for universal synthesis process able to efficiently handle any kind of circuits, regardless their nature, structure, etc.  Genetic programming becomes a candidate, since allsynthesis processes are being done implicitly DDECS’10

11. Cartesian Genetic Programming (CGP) • The circuit is modeled as a 2-dimensional array of programmable elements • The chromosome describes the interconnection and element (gate) types  its size is fixed • The size of the phenotype is variable DDECS’10

12. Cartesian Genetic Programming (CGP) The algorithm • The initial population of 1+  individuals is generated (randomly or using a conventional synthesis) • Evaluate the population • Select the highest scored individual – parent • Use mutation to create  offspring of the parent individual • Create the new population using the parent and its  offspring • If the termination criterion is not satisfied, go to step 2. DDECS’10

13. Cartesian Genetic Programming (CGP) Mutation DDECS’10

14. Cartesian Genetic Programming (CGP) Fitness • Should reflect the circuit (phenotype) size • Must reflect, if the circuit is functionally equivalent to the original • Could reflect the “distance” to the original DDECS’10

15. Cartesian Genetic Programming (CGP) Fitness • Should reflect the circuit (phenotype) size  The number of gates is subtracted from the fitness value • Must reflect, if the circuit is functionally equivalent to the original • Could reflect the “distance” to the original DDECS’10

16. Cartesian Genetic Programming (CGP) Fitness • Should reflect the circuit (phenotype) size  The number of gates is subtracted from the fitness value • Must reflect, if the circuit is functionally equivalent to the original  Invalid individuals are assigned zero fitness • Could reflect the “distance” to the original DDECS’10

17. Cartesian Genetic Programming (CGP) Fitness • Should reflect the circuit (phenotype) size  The number of gates is subtracted from the fitness value • Must reflect, if the circuit is functionally equivalent to the original  Invalid individuals are assigned zero fitness • Could reflect the “distance” to the original  fitness = B + (u.v - g) B – number of correct bits, out of 2n u, v – dimensions of the array g – number of gates DDECS’10

18. Experiments Experimental setup • ABC is used for conventional synthesis • Extended “choice” script used for the circuit optimization • Iterated 1000-times • Mapping into 2-input gates (AND, NAND, OR, NOR, NOR, XNOR) • Cartesian Genetic Programming • v = 1(number of rows) • u = L (number of columns / levels) • Fitness = number of gates, invalid individuals are assigned zero fitness. SAT-based equivalence checking is used •  = 2 (offsprings) • Run for 5 hours DDECS’10

19. Experiments CGP Used as a Primary Optimization Process DDECS’10

20. Experiments CGP Used as a Primary Optimization Process Convergence curves ABC CGP DDECS’10

21. Experiments CGP Used for a Post-Synthesis Optimization • First, the circuit was synthesized using conventional synthesis tools, the “best” conventional synthesis process possible was used • Then it was optimized by CGP DDECS’10

22. Conclusions • A circuit optimization method based on Cartesian genetic programming (CGP) was proposed • CGP is able to implicitly discover “good” circuit structures  it is the sought universal synthesis process • CGP significantly outperforms conventional synthesis tools • This is especially apparent for hard-to-synthesize circuits • CGP may be advantageously used for post-synthesis optimization • The CGP iterative strength is much higher than the iterative strength of the ABC iterative synthesis process  CGP can produce better and better results for a cost of a runtime, whereas ABC gets quickly stuck in a local optimum DDECS’10