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SERDES Introduction

SERDES Introduction. Agenda. I/O Overview SERDES & CDR Fundamental SERDES Measurements How to Evaluate a SERDES Device? High Speed Design Consideration. I/O Overview. Data transmission, is a means of moving data from one location to another.

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SERDES Introduction

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  1. SERDES Introduction

  2. Agenda • I/O Overview • SERDES & CDR Fundamental • SERDES Measurements • How to Evaluate a SERDES Device? • High Speed Design Consideration

  3. I/O Overview • Data transmission, is a means of moving data from one location to another. • There are two main parameters that define how the information is transferred. • Distance, the space between the sending and the receiving systems • speed, the rate at which data has to be passed to the receiving device • As Cable length increases, the speed at which the information is transmitted must be lowered in order to keep the bit error rate down

  4. I/O Types I/O CELL “Single Ended” 2 to 5 volt swing I/O Cell “Differential” 100 to 900mV swing

  5. I/O Interfaces Data rate (per pin) 4Gbit/s XAUI InfiniBand HyperTransport 3Gbit/s 8b/10b Encoded LVDS RapidIO POS-PHY L4 n-LVDS UTOPIA-4 SDR, ZBT, SyncBurst General system logic 2Gbit/s DDR, QDR PCI-X, AGP-2X LVDS PCI, AGP-1X CSIX 1Gbit/s Interface “style” Source- Synchronous, single-ended Source- Synchronous, differential Clock and Data Recovery, differential Conventional, single-ended Conventional, differential

  6. 15 I/O Interface Standards on CMOS Devices LVPECL LVDS PCI-X 10 GTL+ CTT Number of standards HSTL SSTL LVCMOS 1.8 5 LVCMOS 2.5 AGP PCI LVTTL, LVCMOS 3.3 TTL 0 1980 1985 1990 1995 2002 and beyond I/O Timeline • Number of Standards Has Increased Dramatically

  7. Agenda • I/O Overview • SERDES & CDR Fundamental • SERDES Measurements • How to Evaluate a SERDES Device? • High Speed Design Consideration

  8. Parallel vs. Serial Data Transfer Backplane • Parallel data transfer • Multiple lines consume board space • Lines interfere with each other • Each line needs its own termination circuitry • Serial Data Transfer • Fewer lines yields reduced board space • Line interference can be minimized • Uses a fraction of the termination circuitry vs. parallel • No Skew Issues Parallel Parallel Backplane Serial Serial A SERDES provides a means to convert a wide parallel data bus to an equivalent bandwidth Single ‘wire’ serial stream

  9. Why SERDES? • At Very High Speeds, Board-Level Parallel Data Becomes Nearly Impossible to Manage • Variances in Trace Characteristics and Lengths Contribute to Skew: • Data to Data Skew • Clock to Data Skew • Trace count and crosstalk • Backplane Cost is proportional to traces and skew requirements • Logic is Best Performed on Parallel Data • A SERDES Allows the Best of Both Worlds • Serial Data with an Embedded Clock for Distributing Across Backplanes • Parallel Data with Separate Clock for Logic Manipulation FromBackplane Logic ToBackplane CLK CLK SERDES

  10. SERDES Functionality • A SERDES has a: • Transmit section (SERializer) and a • Receive section (DESerializer), also know as a CDR • The transmit portion integrates: • DATA with a • CLOCK signal to modulate the clock pulse (Similar to Manchester encoding) Embedded Clock and Serial Data @ 1 Gbps SERDES Data 9:0 @ 100 MHz 11 Traces Vs 1 (actually 1 pair of traces) CLK 100 MHz

  11. CDR Functionality • The receive portion (CDR) finds both the • underlying clock and the • stream of data from this modulated clock signal. • This is known as: “Clock and Data Recovery (CDR)” VALID CHARACTER DETECT DATA CHARACTER SERIAL BIT STREAM RCV BYTE CLK PHASEGEN Phase 0 clk Phase 1 clk Phase 2 clk -All 8 phases of the pll clk sample the serial stream -Some of the phases will sync to the data stream (I.e. valid character is detected) -clk in the middle of the group of phases that detect valid characters is selected as the RBC Phase 7 clk Pll clk PLL SERIAL BIT STREAM

  12. Next, The Deserializer de-muxes the serial data to the original 10-bit data stream Embedded Clock and Serial Data @ 1 Gbps 11 Traces Vs 1 (actually 1 pair of traces) CDR Functionality…. CDR (Deserializer) Data 9:0 @ 100 MHz Recovered Clock (RBC): 100 Mhz

  13. SERDES & CDR Continued…. SERDES Benefits Include: • Extends the reach at high speeds • Clock & Data are now prone to identical skew which is manageable and more easily recovered • Reduces the overall number of traces on the backplane by ~10x • Significantly Reduces the overall pins per device by ~10x

  14. CDRs and 1’s Density… • The CDR’s PLL must lock onto the embedded clock in the serial stream • This requires a minimum number of 1/0/1 transitions per unit time • A normal data stream however, cannot guarantee a minimum number of transitions…. • We need to somehow manage this….. • This is accomplished usually by 1 of 2 methods: • Encoders/Decoders (8B/10B for Ethernet) or • Scramblers/Descramblers (for SONET)

  15. 00000000 8 bits Lack of ‘1’Cannot Sync Clock 2 bits PLL + fn = 0100100101 00000000 10 bits 8 bits PLL 8B10B Encoding/Decoding Output is 10 bits worth of data, however there is only 8 bits worth of meaningful data Encoding EnsuresProper Transitions toRecover the Clock

  16. DC Balancing • Another Issue for the PLL is DC Shift/Balancing… • A given data stream may have a higher percentage of 1s or 0s over a given time period. • This is called running disparity, which is a measurement of whether the encoded patterns are leaning toward too many ones ( RD+ or positive disparity) or too many zeroes (RD- or negative disparity). • ‘DC Balancing’ is a method to null or eliminate this DC- bias and is part of the 8B10B coding scheme. • The 8B10B encoder selects one of the two possible codes for each datum based on the current state of the disparity (RD+ / RD-). • One code has a higher percentage of 1s to add positive bias • The other code has a higher percentage of 0s to add negative bias

  17. 8B10B Encoding/Decoding Summary… • Converts 8-Bits of Data into a 10-Bit Code • No More Than Five 1’s or 0’s Can be Consecutively Transmitted • Forces Data Transitions Such That an Embedded Clock is Recoverable • Applications • Gigabit Ethernet • 10Gigabit Ethernet • Fibre Channel • 8B10B encoding translates to a 25% bandwidth overhead

  18. 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 0 0 0 1 Scramble Function +1 0 1 1 1 0 0 0 1 SONET Scrambling What is Scrambling and Why is it used? • Ensures Ample Transitioning for Clock Recovery • SONET scrambling is defined as X7+X6+1: No overhead • Certain overhead bytes not scrambled • Could be implemented as: Stream of 127 bytes (X^^7) (X^^6) XOR 8 bit Result

  19. FIFO Alignment • Typically, a SERDES data stream may run at a 3.125 Gbps rate • A Designer may, however require a 6.25 Gbps or higher bandwidth • The designer can chose to Bind 2 or more channels to achieve the higher rate • The Binding of the channels requires that the two SERDES channels be aligned after reception since at 3.125Gbps, 2” of skew corresponds to a Full Signal of delay (1 bit) • A complete SERDES incorporate Multi-channel FIFO alignment and recognition of Comma Characters to achieve the alignment Channel 1 Binding these two channels requires recognition of the alignment point and FIFOs to store and align the data Channel 2

  20. Receive SERDES Receive data Alignment W/8b/10b Decoding 8 38 7 37 W o r d P RCOMMAx(0) RCOMMAx(1) RCOMMAx(2) RCOMMAx(3) K_Ctrl 30 0 Received 0 bit First Received 9 bit Last 8 28 27 7 W o r d Q 8 8 8 8 SERDES Serial STREAM of Data 7 7 7 7 W o r d S W o r d R W o r d Q W o r d P DeMUX BLOCK 0 0 0 0 9 9 9 9 WordS WordR WordQ WordP 0 20 8 18 0 0 0 0 17 7 W o r d R Received First Received Forth Received Third Received Second K_Ctrl SRDBx(7:0) 10 0 8 8 7 7 W o r d S 0 0 MRWDx(39:0)

  21. Agenda • I/O Overview • SERDES & CDR Fundamental • SERDES Measurements • How to Evaluate a SERDES Device? • High Speed Design Consideration

  22. Eye Diagrams • Eye Diagrams Measure the Quality of a Differential Signal • Maximum Eye Height (Vp-p Diff.) and Width Ensures Valid Logic Levels • Long Signal Paths Degrade the Eye Opening at the Receiver End • Time Base is Unit Interval (UI), which is the Inverse of the Clock Frequency • Data falling within the Eye will be Received without Error (BER<1E-12) • Data Pattern Eye-Opening provides a good measure of Signal Quality • Pre-emphasis typically results in a ‘wider’ eye 200mV / 0.4UI Represents the ORCA FPSC SERDES Minimum Receiver Requirement

  23. Eye Diagrams - Lab Experiment • Experiments were conducted to further characterize the SERDES macro cell in the ORT82G5 device and serve as a basis for future device characterization • Test Equipment • ORT82G5 evaluation Board. • Tyco Electronics XAUI backplane with two port cards • HPE3648A Power supplies • HP8133A Clock source • Temptronic E3648A Thermal Soaker • PicoSecond 5575A Bias-T • Agilent 86100A DCA Oscilloscope • Results published in Lattice document, TN1027 (available on web) Eye-Diagram Test Setup

  24. Eye Diagrams - Test Setup Parameters • Conditions • ORT82G5 680 PBGAM plastic ball grid array (wire-bond), -3 speed grade • Power Supply = 1.5 V • Ambient Temperature = 25 degree C • Data Pattern = PRBS 2^32 - 1 with 8B/10B encoding • Varying Data Rate and Pre-Emphasis Levels • PCB Specification • The 2 inch PWB section (port card) is composed of 6 mil wide (1/2 oz. copper thickness) 100 Ohm differential impedance traces • Backplane - 200 mils thick, 14 layers, Nelco 4000-6 FR4 • All signal layers are 10 mil wide (1/2 oz. copper thickness) traces designed for 100 Ohm differential impedance • All signal layers buried and surrounded by GND planes • Port Card - 93 mils thick, 14 layers, Nelco 4000-4 FR4 • Total trace length: 40 inches

  25. Eye Diagrams - ORT82G5 Receiver Eye Patterns An Illustration of Pre-Emphasis Resulting in Larger Eye Openings Baseline Better Best

  26. Eye Diagrams - Drive Length Product Distance (inches) Speed ORT82G5 40 (FR-4) [1] 3.7 GHz ORSO82G5 40 (FR-4) 3.0 GHz [2] ORT8850 75 ft (coax) 622 MHz [1]:Not tested to failure [2]: Simulated value,

  27. PLL Jitter - Clock Jitter • Jitter is critical to the SONET, GbE, FiberChannel and Infiniband protocols yet the equipment suited for SERDES backplane jitter testing is in it’s infancy • Jitter is specified by several components: • (DJ)- Deterministic Jitter • (DCD)-Duty Cycle Distortion • (DDJ)- Data Dependant Jitter • (RJ)- Random Jitter • (PJ)- Periodic/Sinusoidal Jitter • (TJ)- Total Jitter • Specs for Fiberchannel, Infiniband, SFI-5, and XAUI are all different • BERT (Bit Error Ratio Tester) • One of the key pieces of hardware used for generating errors and quantifying the failures. This hardware is used in the testing of jitter specs. • BER (Bit Error Rate) • The ratio of the bits received in error to the total number of bits received

  28. PLL Jitter - Jitter Table Spec Fiber Channel Infiniband SFI-5 XAUI Near/far-end SONET/SDH Lattice part Data Rate 1.0625 Gb/s 2.125 Gbp/s 2.5 Gbp/s 2.5 Gbp/s STM-16/STS-48 (2.488 Gbps) 2.5 Gbps 2.5 Gbp/s (data only, no OH) TX DJ 0.38UI 0.17UI 0.17UI <=0.17UI/0.37UI TX TJ 0.65UI 0.35UI 0.35UI <=0.35UI/0.55UI 0.15 UI 0.17 UI RX DJ tolerance 0.38UI 0.41UI TBD >=0.37UI 0.5 UI RX RJ tolerance 0.22UI RX PJ tolerance 0.10UI (>Baud Frequency / 1667) >0.10UI (>1.875Mhz) RX DJ+RJ tolerance >=0.55UI RX TJ tolerance 0.70UI 0.65UI 0.65UI >=0.65UI >= 0.15 UI 0.734 UI IU =Internal Unit…duration is equal to one clock period PJ mask as a function of frequency for XAUI application

  29. Power - Pre-emphasis & Half Amplitude • Further power savings can be realized by taking the following features into consideration: • Pre-Emphasis • Three settings available (0%, 12.5%, 25%) in FPSC SERDES • Useful feature that compensates for inherent signal loss that occurs over long trace lengths • More pre-emphasis means more power dissipation per SERDES channel • Half-Amplitude Mode • This mode is configurable via a register bit • Used to reduce power dissipation when transmission medium has minimal attenuation

  30. Optimum Power - Pre-emphasis Effects on SERDES Performance* • Pre-Emphasis Effects • Assists in compensating for signal attenuation when driving long trace lengths • When it comes to pre-emphasis, more isn’t always better !

  31. Power - Pre-emphasis Effects on SERDES Performance* • Although pre-emphasis is a valuable tool, certain conditions do not require or more importantly, benefit from the use of pre-emphasis • The diagrams below illustrate the negative effects it may have on signal integrity when it is not required Pre-Emphasis: OFF Pre-Emphasis: ON

  32. Agenda • I/O Overview • SERDES & CDR Fundamental • SERDES Measurements • How to Evaluate a SERDES Device? • High Speed Design Consideration

  33. Eye Diagrams • This is an Eye Diagram • It depicts data transitions • It is a tool to analyze SERDES and backplane performance • It is analogous to the clock and data scope displays used for Tco and Tsu measurements in parallel systems • The Display is persistent • It holds all data points collected • The color indicates how often a location is overwritten • The Height & Width of the Eye translate into the Quality of the signal Data Eye

  34. Receiver Eye-Diagram Graphical View of SERDES Receiver Input Requirements • Unit Interval (UI) is the Normalized Bit Period, I.e., inverse of Clock Frequency: • 1 UI for a 1 Gbps Eye Diagram is 1 nS • 0.4 UI for a 1 Gbps signal is 400 pS (0.4nS) • 0.4 UI for a 2 Gbps signals is 200 pS • Data Falling Outside the Eye Will be Received without Error (BER<1E-12) • Data Pattern Eye-Opening (Receiver End) Provides a Good Measure of Signal Quality • Highlights the Ability of a Data Link for Error-Free Transfer • Specs for an Eye are the • Eye Width, measured in UI or pS • Eye Height, measured in mV

  35. Eye Diagrams • There is Often Confusion Between a Transmitted and Receive Eye Definition and Eye Size… • On the transmit size, the larger the eye opening transmitted, the better • On the receive size, the larger eye opening received the better… • However… • The smaller the requirement for the eye-opening at the receiver, the better

  36. Other Parameters • Bit Rate or Transmit/receive bit clock • The maximum rate at which serial data can be streamed • PLL clock or input clock • The Reference clock frequency required to generate a given serial bit rate • Path length • The maximum length over which data can be transmitted, at a given rate without, or within an acceptable error limit • That is 3.7 Gbps over 34”

  37. Other Parameters • Pre-emphasis • A means to enhance the high-frequency context of the transmitted signal to compensate for limited backplane frequency response • Typically given as: 0%, 12.5%, 25%, etc • More Pre-emphasis Settings is NOT always better No Pre-Emphasis Eye Width:201ps Eye Height: 152.2mV 12.5% Pre-Emphasis Eye Width: 232ps Eye Height: 204.2mV 25% Pre-Emphasis Eye Width: 234ps Eye Height: 268.2mV

  38. A pair of Bias-T connectors at the Scope Bias-T Circuit Digital Scope with Eye-Mask Capability To VTT BIAS=1.5V To Scope To DUT Test Equipment The Bias T Circuit provides the proper 1.5V termination for a CML output buffer. It then removes the DC component for the scope

  39. 1”=170pS Cabling • Cable Matching is Critical • At 3.125 Gbps, the Symbol length is Approximately 300 pS • Typically, Signals travel down cables at 170pS per Inch • This means that a 1” difference in cable length corresponds to a fully destructive difference • This translates to reduced eye height and width and…Increased Error rate, reduced drive length and reduced bandwidth

  40. Agenda • I/O Overview • SERDES & CDR Fundamental • SERDES Measurements • How to Evaluate a SERDES Device? • High Speed Design Consideration

  41. High-Speed PCB Design • Microstrip or Stripline Routing • Microstrip Routing Refers to a Trace Routed on an Outside Layer of the PCB Separated by a Dielectric From the Reference Plane (GND or VCC). • Stripline Routing Refers to a Trace Routed on an Inside Layer With Two Reference Planes Best for SERDES Signals Lowest Delays Higher Capacitance, Longer Delay, Better Impedance control, Cleaner signals

  42. W S W T H PCB Trace Geometry • Differential signal trace-pairs with controlled impedance can be arranged in a number of different configurations: • Edge Coupled Microstrip (Top-layer) • Edge Couple Stripline (Embedded, Preferred for routing SERDES signals) • Broadside Coupled Stripline/Dual Stripline GND/VCC GND/VCC H1 W W T S H2 GND/VCC GND/VCC GND/VCC Broadside Coupled Stripline (Dual-Stripline) Edge Coupled Microstrip Edge Coupled Stripline

  43. 1. Use 100 ohmdifferential impedance pairs on PCB. Controlled impedance lines should be specified in PCB manufacture. 2. Match trace lengths in a pair with tolerance of 20% of the signal rise/fall time. 3. Use connectors that are designed and characterized at the highest data frequency. (Vendors should provide characterization and model data.) 4. Use stripline construction with ground/VDD planes above and below the differential pairs. 5. Use edge-coupled pairs in PCBs, try to avoid broadside coupled pairs. Use 3S separation rule between pairs to avoid crosstalk and excess coupling. Use offset stripline routing to get higher density of differential pairs with each routing layer running orthogonal to each other PCB Design Checklist

  44. High Speed PCB Design – Clock Routing Check List • 1. Avoid Using Serpentine Routing; Clock Traces Should Be As Straight As Possible. • 2. Avoid Using Multiple Signal Layers for Clock Signals. • 3. Avoid Using Vias in the Clock Transmission Line, Since Vias Can Contribute Impedance Change and Reflection. • 4.Route the Clock Trace on the Microstrip (Preferably Top Layer) to Minimize the Use of Vias and Delays, Since Air Is the Dielectric Material. Air Has the Lowest Dielectric Constant (Er = 1). • 5. Place a Ground Plane Next to the Outer Layer to Minimize Noise. If Using the Inner Layer for Routing the Clock Trace, Sandwich the Layer with Ground Planes to Reduce Delay. • 6. Terminate Clock Signals Properly.

  45. Bypass Capacitors – Why? • Very Small Capacitors With Low Series Inductance Are Used to Provide Fast Current for the High Frequency Transitions. • Larger, Slower Capacitors Continue to Supply Current After the High-frequency Capacitors Energy Is Expended. • Existing FPGA Technology Requires Capacitance in Three Frequency Ranges, Referred to As High, Medium, and Low. These Frequencies Span From the 1 KHz Range to the 500 MHz Range. When a Logic Device Switches the Output Structure Is Momentarily at a Low Impedance Across the Power Supply. Each Transition Requires That a Signal Line Be Charged or Discharged, Which Requires Energy. Bypass caps supply the necessary charge during these signal transitions

  46. Bypass Capacitors (Cont’d) • Capacitor Impedance Varies With Frequency • A Capacitor Is Ineffective When the Energy Stored Is Unavailable to the Load Due to the Increase in Effective Impedance. • It is crucial to use several different value capacitors to cover the important frequency areas The higher the capacitance, the lower the frequency point at minimum impedance Capacitors are most effective When their impedance is at it’s lowest

  47. Bypass Capacitors (Cont’d) Capacitor Placement requirements vary with Capacitor Value. The Reason for this dependence on placement Is simple: Inductance in the path From the Capacitor Terminals to the FPGA Power Pins Must Be Kept As Low As possible. Placement of high Frequency caps is more crucial • Capacitor Placement requirements vary with Capacitor Value • High-frequency Bypass Capacitors (.01nF to 10nF) • Mounted Within One Centimeter of the Associated Vcc Pin • Middle-frequency Bypass Capacitors (47 nF to 100 nF Tantalum) • Should Be Mounted Within Three Centimeters of the Vcc Pins. • Low-frequency Bypass Capacitors (470 nF to 3300 nF). • May Be Mounted Anywhere on the Board.

  48. Suggested via location that Connects to a capacitor pad High-Speed Board Designs – Capacitor Layout • Use a Large Via Size to Connect the Capacitor Pad to the Power and Ground Plane to Minimize the Inductance in Decoupling Capacitors. • Use the Wide and Short Trace Between the Via and the Capacitor Pad or Place the Via Adjacent to the Capacitor Pad. • Use Surface Mount Capacitors to Minimize the Lead Inductance • Use Low Effective Series Resistance (ESR) Capacitors. • Each GND Pin/via Should Be Connected to the Ground Plane

  49. High Speed PCB Design (Cont’d) Filtering Noise Checklist • 1. To Diminish the Low-frequency (< 1 Khz) Noise Caused by the Power Supply, Filter the Noise on the Power Lines at the Point Where the Power Connects to the PCB and to Each Device. • 2. Place a 100-µF Electrolytic Capacitor next to the Location Where the Power Supply Lines Enter the PCB. • 3. To Filter High-frequency Noise at the Device, Place Decoupling Capacitors As Close As Possible to Each Vcc and Ground Pair • 4. Placing the Power and Ground Planes in Parallel and Separated by Dielectric Material (FR-4 PCB Layer) Provides Another Level of Bypass Capacitance.

  50. High Speed PCB Design – Ground Bounce Reducing Ground Bounce Checklist: • 1. Add Decoupling Capacitors for As Many VCC/GND Pairs As Possible. • 2. Add External Buffers at the Output of a Counter to Minimize the Loading. • 3. Configure Unused I/O Pins as Outputs Driven Low. This Configuration Acts As a Virtual Ground. Connect This Low Driving Output Pin to the Board’s Ground Plane. • 4. When the Speed Is Not Critical, Turn on the Slow Slew Rate. • 5. Limit the Load Capacitance. • 6. Reduce the Number of Outputs That Can Switch Simultaneously And/or Distribute Them Evenly Throughout the Device. • 7. Move Switching Outputs Close to a Package Ground Pin. • 8. Create Synchronous Designs That Will Not Be Effected My Momentarily Switching Pins. • 9. Place the Power and Ground Pins Next to Each Other. The Total Inductance Will Be Reduced by Mutual Inductance.

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