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Hiep Hong CS 147 Spring 2009

Intel Core 2 Duo. Hiep Hong CS 147 Spring 2009. CPU Chronology. CPU Chronology. Pre-Intel 8086:. Intel 4004 108 KHz 2300 transistors Intel 8008 500-800 KHz 3500 transistors Intel 8080 2 MHz 4500 transistors. CPU Chronology. CPU Chronology. CPU Chronology.

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Hiep Hong CS 147 Spring 2009

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  1. Intel Core 2 Duo Hiep Hong CS 147 Spring 2009

  2. CPU Chronology

  3. CPU Chronology Pre-Intel 8086: Intel 4004 • 108 KHz • 2300 transistors Intel 8008 • 500-800 KHz • 3500 transistors Intel 8080 • 2 MHz • 4500 transistors

  4. CPU Chronology

  5. CPU Chronology

  6. CPU Chronology

  7. Dual-Core or Core 2 Duo • Core 2 Duo is a brand name by Intel. • Dual-Core is a generic description meaning two separate physical cores in one chip package. • Example: Pentium Dual Core, Core Duo and Core 2 Duo.

  8. Intel Core 2 Duo

  9. Intel Core 2 Duo • 64 bit computing. • x86-64 instruction set. • The second generation of dual-core processors from Intel. • Two independent processor cores. • Share up to 6MB of L2 cache. • Developed with a new Architecture called Core Microarchitacture.

  10. Inside Intel Core 2 Duo Die

  11. Intel Core 2 Duo

  12. Sequence of processing

  13. Core Microarchitecture

  14. Core Microarchitecture • Advanced smart cache. • Macro-fusion. • Advanced digital media boost. • Memory disambiguation. • Advanced power gating.

  15. Core Microarchitecture • Advanced smart cache. • Macro-fusion. • Advanced digital media boost. • Memory disambiguation. • Advanced power gating.

  16. Advanced smart cache

  17. Advanced smart cache continued • If one core has minimal cache requirements, the other core can dynamically increase its share of L2 cache •  Reduce cache misses. •  Improve performance.

  18. Core Microarchitecture • Advanced smart cache. • Macro-fusion. • Advanced digital media boost. • Memory disambiguation. • Advanced power gating.

  19. Macro-Fusion

  20. Macro-Fusion continued

  21. Macro-Fusion continued • Enable common pair of instructions to be combined into a single instruction during decoding. • Reduce the total of executed instructions. • Allow processor to execute more instructions in less time. • Increase performance.

  22. Macro-Fusion continued Without macro-fusion With macro-fusion 1 load eax, [mem1] 2 cmp eax, [mem2] 3 jne target 1 load eax, [mem1] 2 cmp eax, [mem2] + jne target

  23. Core Microarchitecture • Advanced smart cache. • Macro-fusion. • Advanced digital media boost. • Memory disambiguation. • Advanced power gating.

  24. Advanced Digital Media Boost • Improve performance when executing Streaming SIMD Extension (SSE, SSE2, SEE3) instructions. • Accelerate video, speech, image, speech and image, photo processing, encryption, financial, engineering and scientific applications.

  25. Advanced Digital Media Boost 128-bit Streaming SIMD Extension (SSE, SSE2, SEE3) instructions.

  26. Core Microarchitecture • Advanced smart cache. • Macro-fusion. • Advanced digital media boost. • Memory disambiguation. • Advanced power gating.

  27. Memory Disambiguation • Accelerate the execution of memory-related instructions. • Load data for instructions about to be executed before all previous store instructions were executed. • Memory-related instructions that can be executed out of order.

  28. Memory Disambiguation continued

  29. Memory Disambiguation continued

  30. Core Microarchitecture • Advanced smart cache. • Macro-fusion. • Advanced Digital Media Boost. • Memory disambiguation. • Advanced power gating.

  31. Advanced Power Gating

  32. Advanced Power Gating continued

  33. Newer and better!

  34. References • http://www.intel.com • http://wikipedia.org • http://www.zdnet.com

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