ECSE-6230 Semiconductor Devices and Models I Lecture 14

1. ECSE-6230Semiconductor Devices and Models ILecture 14 Prof. Shayla Sawyer Bldg. CII, Rooms 8225 Rensselaer Polytechnic Institute Troy, NY 12180-3590 Tel. (518)276-2164 Fax. (518)276-2990 e-mail: sawyes@rpi.edu June 7, 2014 sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html 1

2. Lecture Outline MOS Capacitor Time Dependent Capacitance Measurements Current Voltage Characteristics of MOS Gate Oxides Field Effect Transistor Introduction Field Effect Transistor Basic Output Characteristics

3. Time Dependent Capacitance Measurements During CV measurements, if the gate bias is varied rapidly from accumulation to inversion Depletion width momentarily becomes greater than theoretical maximum for gate biases beyond VT Called deep depletion Drops below Cmin for a transient period Depletion width, over a characteristic time, collapses back to Cmin C-t called Zerbst technique to measure lifetime sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

4. Current-Voltage Characteristics of MOS Gate Oxides Ideally, the gate insulator does not conduct any current For real insulators there can be some leakage current Varies with voltage or electric field across the gate oxide Happens when electric field or temperature is sufficiently high There is a barrier ΔEC, carrier cannot go through the barrier classically but quantum mechanically they can tunnel through sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

5. Tunneling Tunneling is essentially independent of temperature, but strong dependence on applied voltage Fowler-Nordheim tunneling current IFN can be expressed as a function of the electric field in the gate oxide B is a constant depending on mn* and barrier height Direct tunneling Gate oxide becomes so thin the electrons tunnel through What are the implications for modern devices? sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

6. FET (Field Effect Transistor) concept June 7, 2014 Current through two terminals is controlled by voltage at the third terminal Junction FET: control gate voltage varies depletion width of reversed biased pn junction Metal Semiconductor FET: junction is replaced by Schottky barrier Metal-insulator-semiconductor FET: Metal gate electrode separated by an insulator Oxide layer on Silicon is most common (MOSFET) Unipolar (majority carrier) device rather than bipolar June 7, 2014 sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html 6 6

7. FET (Field Effect Transistor) Concept FET family tree Distinguished in the way the gate capacitor is formed

8. MOSFET MOSFET Basic Operation – A field-induced channel to connect two adjacent source and drain junctions. Features: 4th terminal (substrate or backgate terminal) MOS-induced channel Pinchoff near the drain end Parasitic npn sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

9. Water Analogy: MOSFET When the source and drain are level, there is no flow VDS=0 Whatever depth in the canal can be varied by the gear and track (VGS) When the drain is lower than the source, water flows along the canal The flow is limited by the channel capacity, lowering the drain further only increases the height of the waterfall at its edge sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

10. MOSFET Behavior: Types Two types of MOS transistors N-channel MOSFETS (conducting carriers are electrons) Built on p-type substrates so that reverse biased pn junction isolate the conducting channel of nearby devices Positive gate voltages create conducting channel P-channel MOSFETS (conducting carriers are holes) Built on n-type substrates Negative gate voltages create conducting channel Two modes Depletion mode: channel is inverted or on, when the gate to source voltage is zero Enhancement mode: channel is not inverted or off, when the gate to source voltage is zero sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

11. MOSFET Types sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

12. MOSFET Types sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

13. MOSFET Gate controlled potential barrier example Gate voltage to induce the channel is the threshold voltage Fermi level is flat with a potential barrier Positive applied to gate and negative charges form at surface Channel becomes less p-type, reducing the barrier essentially (For enhancement type) sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

14. MOSFET Gate controlled variable resistor example Gate increases, more electrons means more conductive Drain current increases linearly with drain bias More drain current flows, more ohmic voltage drop along the channel Threshold is barely maintained near the drain end called pinch off Saturation region (not affect by drain bias) sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

15. MOSFET I-V Analysis Basic characteristics derived from Gate structure corresponds to an ideal MOS capacitor (no interface traps nor mobile charges) Only drift current will be considered Doping in the channel is uniform Reverse leakage current is negligible Transverse field in the x-direction in the channel is much larger than the longitudinal field in the y direction (Gradual Channel approximation) sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

16. MOSFET I-V Analysis Features of the I-V Characteristics: Linear Region – VGS large, ID varies linearly with VDS Channel connects source and drain regions. MOSFET acts like a gate-controlled resistor. Inversion layer is continuous, no pinch-off. Triode Region – VDS becomes larger, saturating IDS. Channel resistance increases. Saturation Region – VDS gets so large that VDS > VGS Leveling of IDS  IDS,sat Pinch-off region exists at drain. IDS not dependent on VDS sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

17. MOSFET IV Analysis

18. I-V Characteristics Linear Region Onset of Saturation VG>VT, VD≤VG-VT VG>VT, VD=0 VDsat=VG-VT sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

19. I-V Characteristics Channel Length Reduction VG>VT, VD>VG-VT sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

20. Threshold Voltage When the surface potential, s, is at 2 B, the semiconductor surface is at the onset of strong inversion and the gate voltage is at threshold voltage, VT. The threshold voltage is the most important device parameter in any MOS system. Gate voltage required to induce a conducting channel at the surface of the semiconductor

21. I-V Characteristics Inversion charge in the channel ΔΨi is the channel potential with respect to the source end Z is the depth b) no gate bias no drain bias in equilibrium c) equilibrium condition but under a gate bias causing surface inversion In nonequilbirum when both drain and gate bias EFp remains at bulk Fermi level with EFn is lowered toward the drain contact sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

22. MOSFET I-V Analysis Inversion charge is defined by Under ideal conditions the channel current at any y-position is given by Since current has to be continuous and constant throughout the channel, integration from 0 to L Whereυyis the average carrier velocity sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

23. MOSFET Under the assumption of constant mobility where Linear region equations Saturation region, pinch off point sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

24. MOSFET Non-linear region equations: between two extremes Subthreshold region Gate bias is below the threshold and semiconductor surface is in weak inversion or depletion Tells how sharply the current drops to zero with gate bias sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html

25. Example For an n-channel MOSFET with a gate oxide thickness of 10 nm, VT = 0.6V and Z=25μm, L=1μm. Calculate the drain current at VG=5V and VD=0.1V. Repeat for VG = 3V and VD = 5V. Discuss what happens for VD=7V. Assume an electron channel mobility of μn=200 cm2/V-s. sawyes@rpi.edu www.rpi.edu/~sawyes/courses.html