Assignments Documentation Dr Fearghal Morgan. Aim : Capture and implement a digital i mage p rocessing s ystem implemented on the Digilent Xilinx Spartan-3 FPGA development system, controlled by & communicating with host GUI appliedVHDL project overview The project incorporates
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Several exercises form part of the larger appliedVHDL project, as follows:
Follow assignment instructions to complete each element in sequenceSubmission instructions
Project PhasesPhase 1 : displayCtrlr Multiplexed 7-seg display & LED ctrlr
Phase 2 : cascadedBCDCntr&displayCtrlr: Cascaded BCD counter connected to displayCtrlr
Phase 3 :appliedVHDLV1 CSR r/w, display controller, serial I/O
Phase 4 :appliedVHDL CSR r/w, display controller, serial I/O, SRAM r/w controller, SRAM Bus Functional Model (BFM), Datapath controller, DSP function (image processing fn)