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This research aims to simplify product machines and sequential circuits, reducing BDD size and analyzing reachability. By mapping sequential equivalence to combinational equivalence, the study enhances design efficiency and clock skew reduction.
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Flip-Flops Matching of Sequential Circuit Speaker : Adonis Lin Advisor : Chun-Yao Wang 2007.7.31 Department of Computer Science National Tsing Hua University, Taiwan
Outline • Problem Formulation • Research Application • Limits of previous work • Introduction of our work • Conclusion • Future Work
Problem Formulation • Given • A product machine of two sequential circuits • Two separate circuit space (only same PI) • A sequential circuit • One circuit space (overlap fan in cone of FFs) • Initial state • 0 initial sate , X initial state , specific initial state • Objective • Find flip-flop corresponding or constant flip-flop based on initial state
Outline • Problem Formulation • Research Application • Limits of previous work • Introduction of our work • Conclusion • Future Work
Research Application • Simplify product machine & sequential circuit • Use equivalence、complement、constant relation of FFs • It can modify delay of circuit (reduce clock skew) • Reduce size of BDD (reachability analysis) • Use Flip-Flop corresponding prevent BDD size from explosion • Map sequential equivalence checking to combinational equivalence checking
R2 Fan out cone Fan out cone R1 R1 R3 Research Application (cont’d) • How to simplify? • Reduce # of FFs in sequential circuit • Reduce FFs => reduce space size • Timing change (increase or reduce) • EX : R1 = R2 * R3
Outline • Problem Formulation • Research Application • Limits of previous work • Introduction of our work • Conclusion • Future Work
Previous Work (1/2) • Guess Flip-Flop corresponding • Equivalent & Complement relation • Prove Flip-Flop corresponding you guess • Use mathematics induction (M.I.) • If FFC can be found, this FFC is for initial states which matching the rule you guess
Previous Work (2/2) • Found FFC • Three groups • Vg1, Vg2, Vg3 • 8 (23) initial states matching this FFC Initial states must hold this FFC, and this FFC could be proven later !!
Limits of Previous Work • It can not focus on one initial state because of its proving method (M.I.) • It can not find functional relationship • It can only find general FFC which some initial states match • For matching some initial state, only a few FFCs can be found • Practically, we want special FFC for one initial state
M1 S1 S2 S3 X Y S4 S5 M2 Special Example • Example (Five state bits in PM) • Flip-flop matching (Underinitial state : S1=1,S2=S3=S4=S5=0) • S1 = S4 * S5 = S2 * S3 • S2 = S4 • S3 = S5 - - - -
M1 S1 S2 S3 X -X*V + (-V) X -X* V3 + V2 X*V Y X -X* V3 -X*V -X*V + (-V) 1 X* V3 V 0 0 V3 - V - V V V3 V2 - V V2 -V V1 S4 X*V V V3 S5 X*(- (V1+V2)) X*V M2 V2 - V 0 0 - V - V V2 V1 -V V X*V V1 - (V1+V2) - V Use Previous Work With signal V3 Without signal V3 Previous work can not find any FFC, even though begin with proper initial state
Weakness of Previous Work • Because it can not find functional relationship, S1 should be set as V3 instead of (-V1 * -V2) • Even though it can find functional relationship, it still can not find FFC in this case. • Prove (S2 = S4), (S3 = S5), (S1 = S4 * S5 = S2 * S3 ) • Initial state : S1=1, S2=S3=S4=S5=0 (O)……..<1> • Initial state : S1=0, S2=S3=S4=S5=1 (X)……..<2> • Only initial state <1> hold this FFC, but proving this FFC need initial state <1> & initial state <2> hold this FFC - - - -
Outline • Problem Formulation • Research Application • Limits of previous work • Introduction of our work • Conclusion • Future Work
Run Flow • Step.1 • Set all Flip-Flops to specific initial state • Step.2 • Do < pi – time frame > propagation, it stop when no new FFs can be set by pi • Step.3 • Mark FFs (with value 0 or 1) constant FFs under this initial state • Step.4 • Base on FF = f( pi-time frames ) to find relationship between FFs
M1 S1 S2 S3 X Y S4 S5 M2 Example (Time Frame 0) • Find FFC under initial state S1=1, S2=S3=S4=S5=0 1 0 1 0 0 1 0 0 0 1 0
M1 S1 S2 S3 X Y S4 S5 M2 Example (Time Frame 1) • After time frame 0, 3 new FFs set by <PI – time frame> 0 0 0 0
M1 S1 S2 S3 X Y S4 S5 M2 Example (Time Frame 2) • After time frame 1, 2 new FFs set by <PI – time frame>
M1 S1 S2 S3 X Y S4 S5 M2 Example (Time Frame 3) • After time frame 2, no new FFs set by <PI – time frame> • Stop !!
Equivalent ! Equivalent ! FFC Checking (1/2) • Check FFC(1) < Using time frame 1 -- PI > • S1 = • S2 = • S3 = • S4 = • S5 = • FFC(1) • S1 = S4 * S5 = S2 * S3 • S2 = S4 • S3 = S5 - - - -
Equivalent ! Equivalent ! FFC Checking (2/2) • Check FFC(2) < Using time frame 2 -- PI > • S1 = • S2 = • S3 = • S4 = • S5 = • FFC(2) • S1 = S4 * S5 = S2 * S3 • S2 = S4 • S3 = S5 - - - -
Outline • Problem Formulation • Research Application • Limits of previous work • Introduction of our work • Conclusion • Future Work
Conclusion • FFC(2) = FFC(1), this FFC is proved and it will exist for any time frame by M.I. • We can find special FFC under one initial state • We can also find functional relationship • How can we find exact & unique FFC every time frame for checking ?
Outline • Problem Formulation • Research Application • Limits of previous work • Introduction of our work • Conclusion • Future Work
Future Work • Find exact & unique FFC every time frame • Study SAT Solver • Think whether it can apply to our work or not • Study latest paper about our research