Structural Checking of Voltage-Island and Power Gating Low-Power Logic

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971410 吳季恆 971443 張書瑋. Structural Checking of Voltage-Island and Power Gating Low-Power Logic. 摘要.

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971410 吳季恆

971443 張書瑋

Structural Checking of Voltage-Island and Power Gating Low-Power Logic

• 問題描述

• 軟體功能

• ISO_1: Power of isolation control pin can be shut-off whileisolation cell is power-on.

ISO_4: Power domain crossing does not have user-definedisolation cell.

ISO_6: Isolation instance control polarity is differentthan the specification of isolation rule control.

LS_1: Level shifter input voltage value is different thanspecified by level shifter definition.

LS_2: Level shifter output voltage value is different thanspecified by level shifter definition.

• 本程式在完成所有的檢查工作後會將所有的Error Message輸出成Report檔(.rpt)，以下為三個範例

case1: Level shifter input voltage value is different thanspecified by level shifter definition

[LS_1] [Level shifter input voltage value is different than specified by level shifterdefinition][Occurrence: 1]

- [#1] [Pin 'A' of 'sh0' (module LevLH ) is connected to domain TDON (Power Voltage 1V)

Expected voltage domain is 0.8V]

case2: Level shifter output voltage value is different than specified by level shifter definition

[LS_2] [Level shifter output voltage value is different than specified by level shifter definition][Occurrence: 1]

- [#1] [Pin 'Y' of 'sh1' (module LevLH2 ) is connected to domain TDON2 (Power Voltage 1.2V)

Expected voltage domain is 1.5V]

case3: Source and receiver signal voltages of level shifter cell are the same in this path

[LS_4] [Source and receiver signal voltages of level shifter cell are the same in this path] [Occurrence:2]

- [#1] [Level shifter 'sh1' (LevHL) has the same input/output voltage domain in all power modes

Input pin driver: u1_1/u_or2/Y

[#2] [Level shifter 'sh0' (LevLH) has the same input/output voltage domain in all power modes

Input pin driver: u1_1/u_an2/Y

1. Si2 Common Power Format 1.0/1.1. http://www.si2.org/?page=811

2. The IEEE Standard 1801-2009

3. B. Kappor, et al., "Tutorial: SoC Power Management Verification

and Testing," Microprocessor Test and Verification, 2008. Ninth

International Workshop on 8-10 Dec. 2008 Page(s):67 – 72

4. Cadence Conformal Low Power Reference Manual