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## MOSFETs

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**MOSFETs**• Metal Oxide Semiconductor • Transistors • (MOSFETs) Recommended Book: Sedra & Smith, Microelectronics, 4th Edition Boylestad & Nashelsky, Electronic Devices …, 8th Edition. Johns & Martin Analog Integrated Circuit Design MOSFETs**FET Notation**• PMOS (N channel bulk) S B S P N P G G B D D Arrow on the Source The FET is a 4 terminal device • NMOS (P channel bulk) B D D N P N G G B S S MOSFETs**FET Construction**W L • In a MOSFET there are two important physical parameters, • W Width of the channel • L Length of the channel MOSFETs**FET Operation**• The FET is a • Voltage Control Current Source • The current that flows from the drain to the source is dependent on the voltage that is applied to the gate. B D D ID N P N G G S S MOSFETs**FET Operation**• MOSFETs come in two flavours, • enhancement and depletion • In Depletion MOSFETs the channel between the drain and the source already exists and changing the voltage on the gate reduces the channel. These are useful for very low voltage applications. • In Enchancement MOSFETs the channel between the drain and the source does not exist. Changing the voltage on the gate creates and expands the channel. These are the most common type used today and are the only type we’ll study in this course. MOSFETs**FET Operation - Qualitative**VGS NMOS • The current does not flow through any PN junction. • We place a positive voltage on the metal gate. • This attracts negative charge at the top of the bulk region near the gate. • If enough negative charge collects, then the P-type is converted to N type and then we have a path for current to flow from drain to source without ever leaving N-type. • The reverse happens for a PMOS. GATE Metal IS ID N N P Bulk Source Drain MOSFETs**FET Operation - Qualitative**VGS NMOS • When no inversion region exists, then there are two PN junctions. • In normal operation, in an NMOS, the bulk must be lower than or of equal voltage to both the source and the drain or current simply flows from bulk to drain and source. • Assuming normal operation, with no inversion region, to get current from drain to source requires passing through two reverse biased PN junctions. • No current flows without an inversion region. GATE Metal IS ID N N P Bulk Source Drain MOSFETs**FET Operation - Qualitative**NMOS • There is NO dc current path between the metal and either the N or P type semiconductors. • An insulator SiO2 separates the metal from all other conducting substances. • In a MOSFET, • There is no current in or • out of the gate node. GATE Metal Insulator Semiconductor MOSFETs**FET Operation - Quantitative**VGS NMOS • There are only three equations of importance in this idealised MOSFET GATE Metal IS ID N N P Bulk Source Drain MOSFETs**FET Operation - Quantitative**• VT is the minimum gate-source voltage required to obtain strong inversion in the bulk material. • VGS is the voltage difference between the gate and the source. • In an NMOS, VGS is positive. The source voltage is commonly ground. • In a PMOS, VGS is negative, the source voltage is commonly the positive supply voltage MOSFETs**FET Operation - Quantitative**• The degree to which VGS exceeds VT is an important term in most of the expressions for the MOSFET. Commonly this value is given another name, • the overdrive voltage, VOD • the effective gate voltage, Veff • Thus for example, the current equation becomes MOSFETs**FET Operation - Quantitative**• All field effect transistors suffer from a pinch-off effect. • This effect occurs because the width of the conducting channel is dependent on the gate-source voltage. • However current through the channel is resistive and causes a voltage drop between a point in the channel and the source. • Hence the effective voltage between the gate and the point in the channel is less than expected. It is this voltage that determines the width of the inversion region. MOSFETs**FET Operation - Quantitative**• At some point the voltage dropped across the channel is so great that the effective voltage left to cause the inversion region is just sufficient to cause a strong inversion. This is the pinch-off voltage. MOSFETs**FET Operation - Quantitative**• Pinch-off should be considered as a limit on the maximum current that can be passed by the MOSFET despite the driving voltage VDS • If more current was to flow then the channel would pinch-off further, potentially closing the link. • If less current was to flow then the channel would widen, allowing extra current to flow. • In practice, an equilibrium is reached and a maximum saturation current is obtained IDsat. MOSFETs**FET Operation - Quantitative**• To see how this plays mathematically, for a given VGS, the gate-channel voltage must just equal VT, and now assume that pinch-off has just occurred right at the end of the channel at the drain. • We say that at this value of VDS, we are entering the saturated region: MOSFETs**FET Operation - Quantitative**• If we know what value of VDS produces saturation, then we can use this to develop an equation for the maximum current that can flow. VGS-VT • but • therefore MOSFETs**FET Operation - Quantitative**• At low voltages we can simplify the equation that bit more, if we assume that VDS is very small, then we can assume the square of a small number is very small. • The practical reality of this is that the values of VDS for which this is accurate are very small and won’t be of any practical design interest. • However as VDS increases it moves from a region where this is valid to the saturation region, so for a while it still approximately true, but increasingly less true as VDS increases. MOSFETs**FET Operation - Quantitative**MOSFETs**FET Characteristics**MOSFETs**FET Characteristics**MOSFETs**Channel Length Modulation**Metal Source Drain N N L’ L • When we were working out the performance of the MOSFET at high VDS we make the assumption that once pinch-off has occurred then the current hits it’s maximum and stays constant. This is sort of true but there is another mechanism involved that is very significant in modern CMOS designs. MOSFETs**Channel Length Modulation**Metal Source Drain N N VDS(sat)=VGS-VT L’ L VDS- VDS(sat) • Across the channel, only VGS-VT can be dropped because once this voltage has been dropped then the channel ceases to exist. • The remain of the externally applied VDS needs to be dropped across something else, and this is the depletion region that forms near the DRAIN node. MOSFETs**Channel Length Modulation**Metal Source Drain N N L’ L • Across the channel, only VGS-VT can be dropped because once this voltage has been dropped then the channel ceases to exist. • The remain of the externally applied VDS needs to be dropped across something else, and this is the depletion region that forms near the DRAIN node. • In these cases the inverted layer is separated from the drain node by a depletion region. MOSFETs**Channel Length Modulation**Metal Source Drain N N L’ L • Now carriers that have been travelling through the inversion region are travelling so fast that they are injected into the depletion region and are travelling fast enough to get swept across the PN junction. • The carriers at this point are minority carriers at a reverse biased PN junction and hence are swept across the junction if they get close to the junction. The speed of the carriers is such that they do get to within one diffusion length of the junction. MOSFETs**Channel Length Modulation**Metal Source Drain N N L’ L • The practical effect of this is that we do not need to include the L term indicated in the diagram, so the effective L’ left to be traversed is • But the width of the depletion region is dependent on the applied reverse-bias voltage which is some fraction of VDS . It could be worked out from the equations for the depletion width. MOSFETs**Channel Length Modulation**• However this isn’t of great importance, the important fact is that L’ is smaller than L which means that • Which means that the saturation current will increase. • This variation in L has been analysed and it is possible to model this effect with the following modification to the the saturation current equation. is always positive MOSFETs**Channel Length Modulation**• Values of range from 0.005 to 0.03 however is increasing in more modern devices as the geometries get smaller. • Actually has a correspondence to the Early Voltage in BJT’s and actually the same term is used. Early Voltages in FET’s are in the range of 30 to 200 V. The large the early voltage the flatter the saturated region current curve. • The effect of smaller geometries can be quickly demonstrated by the ratio Bigger VA the better. MOSFETs**Channel Length Modulation**Bigger VA the better. MOSFETs**Body Effect**• Another very important second order effect is the body effect. The effect of this is to vary the threshold voltage. • The body effect occurs when the substrate of the transistor (in which the channel forms) is not at the same voltage as the source. MOSFETs**Body Effect**• We’ve assumed so far that the source and substrate have been connected. If they are not connected then they must be reverse biased. • If they are not reversed bias then the PN junction caused by the substrate and source regions will be forward biased and the transistor will not operate. • If they are reversed biased then a larger depletion region will form between the two regions. This will introduce additional depletion region charge which the applied gate voltage will need to overcome to achieve inversion. Thus the threshold voltage will increase. MOSFETs**Body Effect**• Now we said that in an NMOS, the P channel bulk is normally tied to ground. • In a PMOS, the N channel bulk is normally tied to the positive voltage supply and the source if it drops below the positive voltage supply voltage will begin to affect the threshold voltage. • This is to ensure that all substrate-to-channel junctions are always reverse biased or at least unbiased. It helps prevent latch up and unplanned current paths. • If this approach is taken, it avoids having to check continually to ensure that all PN junctions in the MOSFET are correctly biased. A good design tactic. MOSFETs**Body Effect**• Almost always in a design the bulk and source of the transistors are always tied to the same voltage, and normally the most positive (PMOS) or negative voltage (NMOS). • If this were not the case then the source would vary according to the signal on the gate, which would then vary the source-bulk voltage which would affect the threshold voltage which would affect the biasing of the transistor which would affect the gain of the device. This could lead to very poor performance. MOSFETs**Hybrid Model**iG iD Gate Drain + vGS - + vDS - gmvGS rds Source • This is a simplified version of the Hybrid- model presented that was used for the BJT. The most obvious lack is any input resistance, this is because we have an insulated gate and there is no DC current path. • The two remaining important parameters are gm and rds. These can be obtained from the large signal current equation for ID MOSFETs**Small Signal Modeling**• gm is defined as the small signal partial derivative of output current with respect to input voltage, ie • Therefore as MOSFETs**Small Signal Modeling**• Now for the triode region as before it is possible to determine gm. This is a region in which the output current and voltage are acting like a resistor, so gmwill be expected to have a dependency on VDS Same gm as in the saturated region when VDS reaches saturation. MOSFETs**Small Signal Modeling**• It is normal to attempt to rewrite the small signal parameter equations in terms of physical signals that we can control. This allows us to develop a feel for how we can bias the circuit. • gm is most important when we are operating in the saturated (active) region so we’ll look at that. • To keep things simple, we’ll temporarily ignore channel modulation effects. MOSFETs**Small Signal Modeling**• therefore • So • Similarly MOSFETs**Small Signal Modeling**• gm is a very important term and is a major factor in the gain of any circuit, so to recap, let’s consider how it changes with respect to our bias conditions. Increase the gate voltage, you linearily increase the gain. Increase the drain current, you increase the gain by only a square-root factor. Note: MOSFETs**Small Signal Modeling**• The remaining parameter in this simple model is rds. Now rds is defined as the partial derivative of output voltage to output current (as it’s small signal). • If we look at the saturated (active) region where the FET is most commonly used. • therefore MOSFETs**Small Signal Modeling**• Now, if is small, ie a small second order relationship between IDsat and VDS, then we can make a simplifying assumption, that the IDsat current is constant and equal to Idsat. If is small, and it is normally so, then rds is the reciprocal of a small current by a very small number, resulting in a very large small signal resistance. MOSFETs**Small Signal Modeling**• is an indicator of the degree to which the depletion region around the drain gate of the MOSFET modifies the overall channel length. • A high value of indicates a large degree of modulation. • can be reduced linearly by increasing the length of the device that you are designing. So to obtain higher output resistance, use a longer device. MOSFETs**Small Signal Modeling**• In the triode region, we have a different expression for current and it indicates a simple resistor relationship. We’d expect something similar for the small signal resistance. MOSFETs**On Resistance, rDS and RDS**Looking at the two values for rds we can compare their respective values Assume =1 for a moment, and assume VOD=1 as well, then the saturation value is just twice that of the triode resistance. If VOD is less than one, the saturation resistance is larger again due to the inversion effect. If VOD larger then the saturation resistance is smaller. MOSFETs**On Resistance, rDS and RDS**However let’s consider a real circuit, This means that assume VOD = 1 (for simplicity) then the small signal saturation region resistance can be significantly greater, often 100 times greater than in the triode region. MOSFETs**Small Signal Modeling**• Now we have expressions for both parameters in our model in the two areas of interest. • This fully defines the small signal model but it is useful at this point to consider the large signal, or more precisely, the DC value of output resistance that is presented by the transistor. • The small signal output resistance was indicated by the inverse of the slope of the ID vs VDS characteristic curve, but the DC resistance is simply the ratio of the two. This indicates that we’ll be expecting a difference between the AC and the DC resistances for the MOSFET. MOSFETs**On Resistance, RDS**The DC current for small voltages in the triode region is given below Given this, it is possible to work out what the DC resistance RDS would be MOSFETs**On Resistance, RDS**• In the triode region, the small and large signal channel resistances, the drain-source resistance, are approximately the same. • The same slope applies for a small change in the signal as for the overall ratio of overall signal current and voltage. • Thus when operating in this region, the same drain-source resistance can be used for small signal (rDS) and for DC applications (RDS) MOSFETs**On Resistance, RDS**Let’s consider the on resistance for DC current just at pinch-off. At pinch-off, the current is given as But it should be noted that Thus Twice RDS(triode) MOSFETs**On Resistance, RDS**In saturation, the current increases only a little with increase VDS, (assuming channel modulation) so this means that the drain-source resistance is going to rise. The current in the saturation region is given by Thus MOSFETs**On Resistance, RDS**If we look at the circled term, when VDS=VOD then this RDS is the same as that at pinch-off. As VDS increases however the circled term increases linearly, indicating an increase in device resistance. The other term is due to channel modulation and it allows additional current to flow and it effectively reduces the resistance a little but it is the weaker of the two terms. But remember, this is still a small resistance as the currents can be quite large for some selections of VOD and VDS. MOSFETs