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Advanced Computer Architecture Group 2: Long Instruction Word Architecture Implementation

This project focuses on the implementation of an advanced computer architecture using a Long Instruction Word (LIW) design. The system features MultiCore Message Passing, Block Diagram, Hardware Specifications, Results, and various demonstrations like String Reversal and Matrix Multiplications. The architecture includes clustered register files, ALU instructions, branching and message passing handling, special instructions, and more. Two cores are discussed with detailed hardware specifications such as Xilinx Spartan 3AN700 and Altera Cyclone II board. This document presents an overview of the architecture, including instruction set design and performance results.

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Advanced Computer Architecture Group 2: Long Instruction Word Architecture Implementation

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  1. OLIWEOpenLong InstructionWord Element 02211 Advanced Computer Architecture Group 2 Mark Ruvald Pedersen Jaspur Højgård Laust Brock-Nannestad Rasmus Bo Sørensen

  2. Content • Hardware Specifications • Instruction Set Architecture (ISA) • Block Diagram/Architecture • Results • Demonstration

  3. Hardware Specifications • MultiCoreMessagePassing Long Instruction Word Architecture • 4 pipeline stages • Eachcore 4 issue slots wide • 2 ALU slots • 2 Load/Store slots • Eachcore has 16 instructions in pipeline • Memorymapped I/O • Variable instructionwordexecution time • Clustered Register File • Local registers areimplemented in block RAM • Global registers areimplemented in Flipflops

  4. Instruction Set Architecture (ISA) • MIPS-inspiredinstruction set • ALU instructionsareonly register-register instructions • Branchinghandled in ALU Issue slot • MessagePassingHandled in Load/Store Issue slot • Register $0 is always 0, write to this is no-op • Absolute and relative jumps in branching • Specialinstructions: min, max, cmovz, cpuid

  5. Architecture overview

  6. Fetch stage

  7. Decode stage

  8. Write back

  9. Results • Single Core, XilinxSpartan 3AN700 • 2600 slices, 4600 LUTs • Frequency = 66 MHz • DualCore, AlteraCyclone II board • ~9500 LCs • Frequency = 82 MHz • Criticalpath is multiplier and ALU_ID forwarding

  10. Demonstration • String reversal • 99 bottles of beer • Matrix Multiplication – Single Core version • Matrix Multiplication – Dual Core version to be implemented

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