Chap. 7 Counters and Registers. Introduction Chap. 7 의 내용 How FFs and logic gates can be combined to produce different types of counters and registers Divided into 2 parts Part I : principles of counter operation, various counter circuit arrangement, and
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representative IC counters
We’ll break left-to-right convention,
especially in counter diagrams
If 2N = X, do not do steps 2 and 3
the outputs of these FFs to the NAND inputs.
counter : Fig. 7-9
Clear ( C0 )
* FF 개수 증가
The total propagation delay
증가하고 fmax 감소
such that they are HIGH only when the outputs of
all lower-order FFs are in the HIGH state
ABC = (J = K)
Design in 7-14
AB =( J = K)
a four input AND gate whose inputs are A, B, C, and D
(c) Determine fmax for the MOD-32 parallel counter
5, 4, 3, 2, 1, 0, 5, 4, 3, 2, 1, ...
4 distinct states
(Initial Content of the 74ALS164 = 00000000)
Q0 - Q7으로 출력됨(따라서 Transparent Latch 라고도 함)
p. 333, Fig. 7-12 참고