Memory/Cache Optimization

2. Memory/Cache Optimization Lochana Narayanan Suchitra Chandran

3. A Distributed BIST Control Scheme for Complex VLSI Devices Yervant Zorian AT&T Bell Laboratories Princeton, NJ, 08540

4. Introduction • The problem in today’s VLSI devices. • Power, noise and area overhead. • Solution – BIST! (Built in self test)

5. How BIST does it? • It is used at all levels and reused at all consecutive levels. • Possible only when if BIST features are included in devices. • Devices are the building blocks – higher BIST levels are built. • So, device level BIST realization takes into account the BIST requirements of all levels, device, MCM, board, system. • These requirements affect the BIST Execution Scheduling, hence the need for BIST Control Network.

6. Existing Scheduling approaches • Focus on optimizing the test time for random logic blocks. • Problems in executing BIST in parallel : • Power and noise dissipation • Higher activity rate • Overpass the device package limits. • New BIST scheduling process : • Power dissipation less • Global optimization – block type, device floor plan and test time.

7. New BIST Control Scheme • Simplifies BIST Execution • Autonomous embedded block • Simple and uniform interface protocol to communicate b/w controller and embedded blocks • Distributed architecture • Minimize routing cost – control elements placed close to BIST blocks • Minimal control signals

8. BIST Scheduling Process • Analysis process where no hardware modifications are allowed. • Prior to scheduling, 2 analysis processes are performed: • Device partitioning • BIST scheme selection

9. Partitioning and BIST Control • ASIC Z is a 132 pin standard device • Partitioned into ten blocks • Based on different criterion : - Structural types – 4 RAMs 2 ROMs and Register File (RF) -Random Logic blocks – RL1 and RL2 - High frequency blocks – RL3

10. Partitioning and BIST Control Contd. • Each block requires • Test Pattern Generator (TPG) • Output Data Evaluator (ODE) • BIST Resource Controller (BRC) • RL1 and RL2 – Pseudo random based TPG and polynomial based ODE • RF and 4 RAMs – 100% fault coverage TPG ODE(RF) - provides zero loss of fault coverage ODE(RAM)- performs output data comparison and space compaction • 2 ROMs – TPG and ODE -> perform exhaustive test sets

11. BIST Scheduling attributes • Power dissipation of each block • Adjacency of blocks • Type of each block • Test time

12. Power Dissipation Analysis • BIST is executed at system clock rate • Adv. : full benefit is obtained • Disadv. : higher activity rate -> excess power dissipation • P=F.N.PG • F : Frequency • N : Block size = number of grids • PG : number of watts per active grid andactivity rate (0.5 for BIST modes) • Different modes : Normal, BIST active and BIST idle • BIST Active – during execution of a block • BIST Idle – during periods when it waits for other blocks to execute BIST. • Total power dissipation = power from each block + power from input and output buffers.

13. Power Dissipation Analysis Contd. • Package limit of ASIC Z is 900mW. • Based on the values in the table, the device power dissipation for parallel BIST execution is 2.332W. • Hence BIST Scheduling for power optimization is necessary.

14. ii. Grouping and Ordering • Create groups and proper sequence of each stage – BIST Execution • Grouping and Ordering is dependent on the physical distribution of the blocks on the floor plan of a device. • Grouping is done based on 2 conditions : • BIST power dissipation has to be less than device limit • Blocks in a group have to be physically adjacent on floor plan. • A profile which is the result of grouping and sequencing at device level is in a matrix format : • Bij - block, i – single BIST stage, j – number of blocks • For our example, we have :

15. iii. Sharing and Test Time Optimization • Sharing reduces hardware area by reducing redundancies. • Sharing between blocks of same type: RAMs, random logic, since their BRCs are identical and TPGs and ODEs are different in parameters. • Combine Boundary Scan with pseudo random TPGs on one hand and with ODEs on the other. • Test time is a limited amount of time that is dedicated per device. • BIST Execution takes only a minor fraction of the total test time as the other tests are far more time consuming.

16. BIST Control Architecture • Control operation has 4 functions: • External access to device level BIST. • Control of BIST facilities of each block. • Control of device BIST. • Transfer of BIST response data. • These functions are realized in 3 types of hierarchical controllers : • External BIST Access Port • BIST Resource Controllers (BRCs) • BIST Control Network.

17. External BIST Access Port • Boundary Scan TAP is the external access port for the device BIST. • For simple tests – use 1 controller, TAP finite machine and boundary scan instructions. • For complex tests – separate controllers are required for each one of BIST control functions. • BIST execution and BIST response data transfer are done via BS TAP – no additional pins dedicated for external BIST access.

18. BIST Resource Controllers • Individual BRCs have to be allocated because : • Number of blocks is in continuous growth. • BIST schemes of each block are different. • They are customized – TPG and ODE • Sharing of non identical BRCs • low complexity – FSM • Not cost effective

19. BIST Control Network • Executes the device BIST based on predetermined schedule. • Functions : • Receives BIST execution via TAP and provides activation signals. • Collects and transfers BIST response when BIST completes. • Advantages : • Division of control network – each function controls subsequent BIST operation.

20. Distributed BIST Control Network • Centralized controllers for device level BIST control. • Problems : • Routing area and number of control lines increase with the increase in the number of BRCs • For smaller number of blocks, centralized BIST control is possible. • Optimizes cost of control lines.

21. SBRIC Finite State Machine • Distributed network has control elements called Scheduled BIST Resource Interface Controllers

22. BIST control network • Disadvantages : Accumulates signatures of all BISTed blocks to a common compactor – loss of diagnostic information. • Advantages : Provides not only group but also block level information.

23. Conclusions - Generic BIST scheduling process and effective BIST control architecture. - Scheduling provides power optimization. - Control architecture provides autonomous BIST activation and capability to identify failed blocks. Future Works- BIST network with additional diagnostic capabilities can be used for reconfiguration and repair operation.- Development of scheduling processes that take into account multi level test restrictions.

24. A Hybrid BIST Architecture and its Optimization for SoCTesting GertJervan, ZeboPengRaimundUbar, Helena Kruus Linköping University, Sweden Tallinn Technical University, Estonia

25. A Hybrid BIST Architecture and its Optimization for SoC Testing OVERVIEW 25/42

26. A Hybrid BIST Architecture and its Optimization for SoC Testing INTRODUCTION INTRODUCTION 26/42

27. A Hybrid BIST Architecture and its Optimization for SoC Testing BIST 27/42

28. A Hybrid BIST Architecture and its Optimization for SoC Testing HYBRID BIST 28/42

29. A Hybrid BIST Architecture and its Optimization for SoC Testing APPROACH OF THE PAPER 29/42

30. A Hybrid BIST Architecture and its Optimization for SoC Testing TARGET HYBRID BIST ARCHIETECTURE 30/42

31. A Hybrid BIST Architecture and its Optimization for SoC Testing TARGET HYBRID BIST ARCHIETECTURE 31/42

32. A Hybrid BIST Architecture and its Optimization for SoC Testing COST of HYBRID BIST 32/42

33. A Hybrid BIST Architecture and its Optimization for SoC Testing COST of HYBRID BIST CGEN : cost related to the time for generating L pseudorandom test patterns (number of clock cycles) CMEM : related to the memory cost for storing S pre-computed test patterns to improve the pseudorandom test set Β, α : constants to map the test length and memory space to the costs of the two parts of the test solutions to be mixed. 33/42

34. A Hybrid BIST Architecture and its Optimization for SoC Testing COST CALCULATION FOR PSEUDORANDOM TEST BIST Analysis Data 34/42

35. A Hybrid BIST Architecture and its Optimization for SoC Testing COST CALCULATION FOR STORED TEST ALGORITHM 1 Notations used 35/42

36. A Hybrid BIST Architecture and its Optimization for SoC Testing COST CALCULATION FOR STORED TEST ALGORITHM 2 Notations used 36/42

37. A Hybrid BIST Architecture and its Optimization for SoC Testing TABU SEARCH 37/42

38. A Hybrid BIST Architecture and its Optimization for SoC Testing RESULTS L : length of pseudorandom sequence C: fault coverage CT : total cost of BIST S : number of test patterns generated by deterministic ATPG to be stored in BIST TG : the time (sec) needed for ATPG to generate the deterministic test set TA: the time(sec) needed for carrying out manipulations on fault tables N : number of efficient patterns in the pseudorandom test sequence T1,T1 : the time (sec) needed for calculating the cost curve by Algorithms 1 and 2 T3 : the time (sec) to find the optimal cost by using Tabusearch Ts: number of calculations in Tabu search Acc: percentage accuracy of Tabusearch solution compared to solution found from cost curve 38/42

39. A Hybrid BIST Architecture and its Optimization for SoC Testing RESULTS Percentage of test patterns in the optimized test sets compared to the original test sets 39/42

40. A Hybrid BIST Architecture and its Optimization for SoC Testing RESULTS Cost comparison of different methods. Cost of pseudorandom test is taken as 100% 40/42

41. A Hybrid BIST Architecture and its Optimization for SoC Testing SUMMARY 41/42

42. A Hybrid BIST Architecture and its Optimization for SoC Testing FUTURE WORK 42/42

43. A Hybrid BIST Architecture and its Optimization for SoC Testing QUESTIONS