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  1. ريزپردازنده ها Microprocessors Spring 2005

  2. Books • The Z80 Microprocessor , Hardware , Software programming & interfacing • Author: Burry B. Brey • Translator: Hossein Nia • Publisher: Astane Ghodse Razavi(Beh Nashr

  3. Books • Microcompiuter and Microprocessor : the 8080 , 8085 , Z-80 Programming , interfacing and trubleshooting • Publisher: NassPub.Date: 1381Edition Turn: 3ISBN: 964-6264-43-4-3Pages: 719Author: John E . UffenbeckTranslator: Mahmmod Dayani

  4. Books • The 80x86 IBM PC and compatible computers (Design and interfacing of the IBM PC PS and compatible)Publisher: BaghaniPub.Date: 1379Edition Turn: 2ISBN: 964-91532-3-3Pages: 760Author: Mohammad Ali . Mazidi Janice Gillispie . MazidiTranslator: Dr. Sepidnam

  5. Books • Microcontroller 8051Publisher: BaghaniPub.Date: 1380ISBN: 964-7343-00-0Pages: 380Author: Mohammad ali Mazidi Jonis Glispi MazidiTranslator: Dr. Sepidnam

  6. Books • The 8051 MicrocontrollerPublisher: BaghaniPub.Date: 1380Publishing Turn: 5Edition Turn: 3ISBN: 964-91532-2-5Pages: 383Author: Iscott Makenzi Translator: Rezaei Nia ,Darbandi Azar

  7. Intruduction • Microprocessor (uP)(MPU) • A uP is a CPU on a single chip. • Components of CPU • ALU, instruction decoder, registers, bus control circuit, etc. • Micro-computer (u-Computer) • small computer • uP + peripheral I/O + memory specifically for data acquisition and control applications • Microcontroller (uC) • u-Computer on a single chip of silicon

  8. uP vs. uC • A uP • only is a single-chip CPU • bus is available • RAM capacity, num of port is seletable • RAM is larger than ROM (usually) • A uC • contains a CPU and RAM,ROM ,Prepherals, I/O port in a single IC • internal hardware is fixed • Communicate by port • ROM is larger than RAM (usually) • Small power consumption • Single chip, small board • Implementation is easy • Low cost

  9. uP vs. uC – cont. • Applications • uCs are suitable to control of I/O devices in designs requiring a minimum component • uPs are suitable to processing information in computer systems.

  10. uP vs. uC – cont. • uC is easy to use and design. • Only single chip can be a complete system • interfacing to other devices, • for example, motors, displays, sensors, and communicate with PC. • In contrast, similar system that builds from uP would require a lot of additional units, • such as RAM, UART, I/O , TIMER and etc.

  11. uC is a Reusable Hardware • Logic circuit provides limited function for one single design. In order to change circuit’s functionality, we need to redesign the circuits. • uC can reprogram and change functionality of every port, input to output or digital to analog on the fly.

  12. uCs • Many uCs are existing right now. • 8051, 68HC11, MSP430, ARM series, and etc. • We may widely divide it with how it is designed • RISC/CISC architecture. • What is the main difference between RISC/CISC? • Does it make any difference to our application?

  13. The Microprocessor (MPU) • The uP is the ‘brain of the microcomputer’ • Is a single chip which is capable of • processing data • controlling all of the components which make up the microcomputer system • µP used to sequence executions of instructions that is in memory • uP Fetch , Decode , and Execute the instruction • The internal architecture of the microprocessor is complex.

  14. The Microprocessor (MPU) • microprocessor (MPU) typically contains • Registers: Temporary storage locations for program instruction or data. • The Arithmetic Logic unit (ALU): This part of the MPU performs both arithmetic and logical operations • Timing and Control Circuits: that keep all of the other parts of system (Regs, ALU, memory & I/O) working together in the right time sequence

  15. Microcomputers • All Microcomputers consist of (at least) : • 1. Microprocessor Unit (MPU) • 2. Program Memory (ROM) • 3. Data Memory (RAM) • 4. Input / Output ports • 5. Bus System • (and Software) • MPU is the brain of microcomputer

  16. Microcomputers

  17. The Input/Output (I/O) System • I/O is the link between the MPU and the outside world. • An input port is a circuit through which an external device can send signals (data?) to the MPU. • An output port is a circuit that allows the MPU to send signals (data?) to external devices. • I/O ports connect both digital and analogue devices by DAC and ADC

  18. Bus • A Bus is a common communications pathway used to carry information between the various elements of a computer system • The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB) though which binary information is transferred from one part of the microcomputer to another • The individual subsystems of the digital computer are connected through an interconnecting BUS system.

  19. Bus • There are three main bus groups • ADDRESS BUS • DATA BUS • CONTROL BUS

  20. Data Bus • The Data Bus carries the data which is transferred throughout the system. ( bi-directional) • Examples of data transfers • Program instructions being read from memory into MPU. • Data being sent from MPU to I/O port • Data being read from I/O port going to MPU • Results from MPU sent to Memory • These are called read and write operations

  21. Address Bus • An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer • The Address Bus is used to transmit the address of the location to the memory or the I/O port. • The Address Bus is unidirectional ( one way ): addresses are always issued by the MPU.

  22. Control Bus • The Control Bus: is another group of signals whose functions are to provide synchronization ( timing control ) between the MPU and the other system components. • Control signals are unidirectional, and are mainly outputs from the MPU. • Example Control signals • RD: read signal asserted to read data into MPU • WR: write signal asserted to write data from MPU

  23. Main memory • The duties of the memory are : • To store programs • To provide data to the MPU on request • To accept result from the MPU for storage • Main memory Types • ROM : read only memory. Contains program (Firmware). does not lose its contents when power is removed (Non-volatile) • RAM: random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values

  24. Read-Only Memory • uP can read instructions from ROM quickly • Cannot write new data to the ROM • ROM remembers the data, even after power cycled • Typically, when the power is turned on, the microprocessor will start fetching instructions from the still-remembered program in ROM (bootstrap )

  25. Available ROMs • Masked ROM or just ROM • PROM or programmable ROM(once only) • EPROM (erasable via ultraviolet light) • Flash (can be erased and re-written about 10000 times, usually must write a whole block not just 1 byte or 2 bytes, slow writing, fast reading) • EEPROM (electrically erasable read-only memory, also known as EEROM—both reading and writing are very slow but can program millions of times…useless for storing a program but good for say configuration information.

  26. : Output Enable connect to RD of uP ROM A0 D0 A1 D1 A2 D2 m+1 bit Address n+1 bit Data Am Dn ROM PROM EEPROM Capacity : : Chip Enable to Address decoder

  27. Timing Diagram for a Typical ROM A0-Am D0-Dn OE falls to data valid Addr valid to data valid

  28. 32 kbit 4 kbyte 16 kbit 2 kbyte 64 kbit 8 kbyte 27XX EPROM PGM and VPP are used to programming

  29. 27XXX EPROM 128 kbit 16 kbyte 256 kbit 32 kbyte 512 kbit 64 kbyte 1024 kbit 128 kbyte

  30. 16 kbit 2 kbyte 4096 kbit 512 kbyte 64 kbit 8 kbyte 1026 kbit 128 kbyte 256 kbit 32 kbyte 28XX E2PROM

  31. RAM (Random Access Memory) • The uP can read thedata from RAM quickly, • The uP can write new data quickly to RAM • RAM forgets its data if power is turned off • Two type of is available : • Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for cache , no refresh • Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh.

  32. : Write signal connect to MemWR of uP : Chip Select to Address decoder RAM(Static) A0 D0 A1 D1 A2 D2 m+1 bit Address n+1 bit Data Am Dn Capacity : RAM Data bus is Bidirectional : Read signal connect to MemRD of uP

  33. Session 2 • Microprocessors • History • Data width • 8086 vs 8088 • 8086 pin description • Z80 Pin description

  34. Microprocessors • Microprocessors come in all kinds of varieties from the very simple to the very complex • Depend on data bus and register and ALU width uP could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit • We will discuss two sample of it • Z80 as an 8-bit uP • and 8086/88 as an 16-bit uP • All uPs have • the address bus • the data bus • RD, WR, CLK , RST, INT, . . .

  35. History

  36. Internal and External Bus • Internal bus is a pathway for data transfer between registers and ALU in the uPs • External bus is available externally to connect to RAM, ROM and I/O • Int. and Ext. Bus width may be different • For example • In 8088 Int. Bus is 16-bit , Ext. bus is 8-bit • In 8086 Int. Bus is 16-bit , Ext. bus is 16-bit

  37. 8086 vs 8088 Only external bus of 8088 is 8_bit 8_bit Data Bus 20_bit Address 16_bit Data Bus 20_bit Address 8088 8086

  38. 8086 Pin Assignment

  39. 8086 Pin Description Vcc (pin 40) : Power Gnd (pin 1 and 20) : Ground AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus MN/MX’ (input) : Indicates Operating mode READY (input , Active High) : take uP to wait state CLK (input) : Provides basic timing for the processor RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately terminate its present activity. TEST’ (input , Active Low) : Connect this to HIGH HOLD (input , Active High) : Connect this to LOW HLDA (output , Active High) : Hold Ack INTR (input , Active High) : Interrupt request INTA’ (output , Active Low) : Interrupt Acknowledge NMI (input , Active High) : Non-maskable interrupt

  40. 8086 Pin Description DEN’ (output) : Data Enable. It is LOW when processor wants to receive data or processor is giving out data (to74245) DT/R’ (output) : Data Transmit/Receive. When High, data from uP to memory When Low, data is from memory to uP (to74245 dir) IO/M’ (output) : If High uP access I/O Device. If Low uP access memory RD’ (output) : When Low, uP is performing a read operation WR’ (output) : When Low, uP is performing a write operation ALE (output) : Address Latch Enable , Active High Provided by uP to latch address When HIGH, uP is using AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as address lines

  41. Z80 CPU Pin Assignment

  42. Z80 Pin Description A15-A0 : Address bus (output, active high, 3-state). Used for accessing the memory and I/O ports During the refresh cycle the I is put on this bus. D7-D0 : Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts. RD: Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O WR: Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.

  43. Z80 Pin Description MREQ Memory Request (output, active Low, 3-state). Indicates memory read/write operation. See M1 IORQ Input/Output Request(output,active Low,3-state) Indicates I/O read/write operation. See M1 M1 Machine Cycle One (output, active Low). Together with MREQ indicatesopcode fetch cycle Together with IORQ indicates an Int Ack cycle RFSH Refresh (output, active Low). Together with MREQ indicates refresh cycle. Lower 7-bits address is refresh address to DRAM

  44. Z80 Pin Description • INT • Interrupt Request (input, active Low). • Interrupt Request is generated by I/O devices. • Checked at the end of the current instruction • If flip-flop (IFF) is enabled. • NMI • Non-Maskable Interrupt • (Input, negative edge-triggered). • Higher priority than INT. • Recognized at the end of the current Instruction • Independent of the status of IFF • Forces the CPU to restart at location 0066H.

  45. Z80 Pin Description • BUSREQ • Bus Request (input, active Low). • higher priority than NMI • recognized at the end of the current machine cycle. • forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp. • BUSACK • Bus Acknowledge (output, active,Low) • indicates to the requesting device that address, data, and control signals MREQ, IORQ, RD, and WR have entered their high-impedance states.

  46. Z80 Pin Description • RESET • Reset (input, active Low). • RESET initializes the CPU as follows: • Resets the IFF • Clears the PC and registers I and R • Sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state And all control output signals go to the inactive • state. • must be active for a minimum of three full clock cycles before the reset operation is complete.

  47. Z80 CPU

  48. Z80 Programming Model

  49. Register Set • A :Accumulator Register • F : Flag register • Two sets of six general-purpose registers • may be used individually as 8-bit A F B C D E H L (A’ F’ B’ C’ D’ E’ H’ L’) • or in pairs as 16-bit registers AF BC DE HL (AF’ BC’ DE’ HL’) • The Alternative registers (A’ F’ B’ C’ D’ E’ H’ L’) not visible to the programmer but can access via: • EXX (BC)<->(BC') , (DE)<->(DE') , (HL)<->(HL') • EX AF, AF’ (AF)<->(AF') what is this instruction useful for?

  50. Register Set(cont) • 4 16-bit registers hold memory address (pointers) • index registers (IX) and (IY) are 16-bit memory pointers • 16 bit stack pointer (SP) • Program counter (PC) • Program counter (PC) • PC points to the next opcode to be fetched from ROM • when the µP places an address on the address bus to fetch the byte from memory, it then increments the program counter by one to the next location • Special purpose registers • I : Interrupt vector register. • R : memory Refresh register