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ARA I design/IRS-testing/Antenna Reoprt

Chih-Ching Chen 2010/07/29. ARA I design/IRS-testing/Antenna Reoprt. Working items…. ARA weekly phone meeting Antenna design / XFDTD 7.1 study IRS ADC Chip Testing. ARA Weekly Phone Meeting. Every 8:30 am Tuesday Reading many ARA internal documents form

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ARA I design/IRS-testing/Antenna Reoprt

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  1. Chih-ChingChen 2010/07/29 ARAIdesign/IRS-testing/AntennaReoprt

  2. Workingitems… • ARAweeklyphonemeeting • Antennadesign/XFDTD7.1study • IRSADCChipTesting

  3. ARAWeeklyPhoneMeeting • Every8:30amTuesday • ReadingmanyARAinternaldocumentsform ARAwebsite(Petertoldustheaddressandpassword) Include: ARA-testbed report, ARA-I design ( antenna , power system, data acquisition, drilling..)

  4. Antenna

  5. Peter’s V-pol Antenna

  6. Peter’s H-pol Antenna From Peter’s slide

  7. Peter’s H-pol Antenna From Peter’s slide

  8. Peter’s H-pol Antenna Anisotropic!! From Peter’s slide

  9. Peter’s H-pol Antenna Anisotropic!! From Peter’s slide

  10. Learning XFDTD 7.1 • Installed in Peter’s server • Reproduce Peter’s result

  11. IRSADCChipTesting • IRSChip–theheartofARADAQsystem • Pedestal (offset) • Voltage calibrate table (nonlinear) • Impedance ( S11 ) • Bandwidth • Sampling rate: 1~2 GHz Sample rate - ( PED and V-cal table also change )

  12. ErrorofAnalog-to-Digital Converter ADC : Analog Input – Digital Output 010110011 101010001 011110101 101110101 offset, nonlinear is sample Δt uniform? Δt Readout ADC counts Input voltage time

  13. Software – Firmware stracture Software command Testing signal FPGA IRS ADC VHDL

  14. Software Graphic User Interface 64 Sample points

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