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Chapter 5

Chapter 5. Internal Memory 5.1 Semiconductor Main Memory 5.2 Error Correction 5.3 Advanced DRAM. Semiconductor Memory Types. Semiconductor Memory. RAM Random Access Memory Misnamed all semiconductor memory is random access (well … flash?) Read/Write

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Chapter 5

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  1. Chapter 5 Internal Memory 5.1 Semiconductor Main Memory 5.2 Error Correction 5.3 Advanced DRAM SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  2. Semiconductor Memory Types SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  3. Semiconductor Memory • RAM Random Access Memory • Misnamed • all semiconductor memory is random access (well … flash?) • Read/Write • Volatile (lose power – lose memory contents) • Temporary storage • static or dynamic SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  4. Memory Cell Operation SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  5. Dynamic RAM • Bits stored as charge in capacitors  charge “leaks” • level of charge determines value • need refreshing even when powered • Pro: simple, small, inexpensive • Con: need refresh circuits, slow • Main memory capacitor is an “electrical sponge” Analog Device! SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  6. Dynamic RAM Structure ‘High’ Voltage at Y allows current to flow from X to Z or Z to X one transistor and one capacitor per bit Y X Z + SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  7. DRAM Operation • Address line active  transistor switch closed and current flows • Write • data signal to bit line: High  1 Low  0 • address line active  transfers charge from bit line to capacitor • Read • address line active • transfer charge from capacitor to bit line (then to amplifier) • capacitor charge must be restored ! SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  8. Static RAM Digital Device! • Bits stored in transistor “latches”  no capacitors! • no charge leak, no refresh needed • Pro: no refresh circuits, faster • Con: more complex construction, larger per bit more expensive • Cache transistors “switch” faster than capacitors charge ! SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  9. Static RAM Structure 1 “NOT” six transistors per bit (“flip flop” will see in 97.2xxx) 1 0 1 0 = example 0/1 0 1 0 SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  10. Static RAM Operation • Transistor arrangement (flip flop) has 2 stable logic states • Write • signal bit line: High  1 Low  0 • address line active  “switch” flip flop to stable state matching bit line • Read • address line active • drive bit line to same state as flip flop no need for refresh! SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  11. SRAM v DRAM Summary • Both volatile – need power to preserve data SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  12. Read Only Memory (ROM) • Permanent storage  Nonvolatile • Boot program • Systems programs (BIOS) • Embedded application program • Library subroutines • Function tables SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  13. Types of ROM • ROM written during manufacture • very expensive for small runs, cheap for large runs • PROM Programmable (once) • need special equipment to program • must program before placing in computer SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  14. Read “mostly” Memory (Nonvolatile) • Erasable Programmable (EPROM) • erased by UV, special equipment to program • must program before placing in computer • must remove from computer to modify • Electrically Erasable (EEPROM) • at word level • takes much longer to write than read • Flash memory • erase blocks of memory electrically modify in computer via bus SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  15. Organizing Memory • memory components must often be grouped together to provide useful configurations • e.g. one component might implement a 2K array of 1-bit elements • organize 8 components together to provide a 2K array of bytes total = 2K x 8-bit 2K x 1-bit … address data control SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  16. What’s a MUX? • multiplexer • acts like a switch between several inputs and a single output select if select = 0 then output = A if select = 1 then output = B 2-to-1 MUX A Output B SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  17. What’s a DEMUX? • demultiplexer • decodes inputs to activate an output 2-to-4 DEMUX O0 A O1 O2 B O3 SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  18. 16MBit DRAM Organisation (Example) • one chip: 2048 x 2048 x 4bit array (4M x 4bit array) • Reduces number of address pins • use 11 pins to address ( 211 = 2048 ) • Multiplex row address and column address SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  19. Refreshing • Refresh circuit included on chip • Disable chip • Count through rows • Read & Write back • Takes time • Slows down apparent performance SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  20. Typical 16 Mb DRAM (4M x 4) RAS = Row Addr. Select CAS = Column Addr. Select WE = Write Enable OE = Output Enable 2 k x 2 k = 4 M nybble SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  21. How to organize into a 16MByte Module? CAS# 4M x 4 data (8) RAS# high nybble (4) 11 bits address (24) low nybble (4) mux 11 bits address (11) demux byte select 2 bits SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  22. data = byte data = nybble Packaging SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  23. 8 x 1-bit modules = byte Example:256kByte Module Organisation 218 = 256k . . . SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  24. Groups Extend Example to 1 Mbyte Module A B C D 256 k 256 k 256 k 256 k SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  25. Error Correction • Hard Failure • Permanent defect • Soft Error • Random, non-destructive • No permanent damage to memory • Detected using Hamming error correcting code SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  26. Error Correcting Code Function SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  27. e.g. Single Bit Error Detection • Add one “parity bit”, K=1 • Compute value of parity bit as follows (this is f): • Count number of 1 bits in data part of a word • If this count is even, parity bit is 0, else parity bit is 1 • Can detect single bit errors, but multiple bit errors may go undetected • Not enough info. to correct errors, i.e. there is no “Corrector” module SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  28. e.g. Correction of 4-bit words • M=4, and it turns out we need K=3 • With 4 bit data words, have following combinations • 00002, 00012, 00102, 00112, …, 11102, 11112 • For each data word abcd2, mem computes 3 parity bits g, h, i: A Each parity bit chosen so the number of 1s in its circle is even, i.e. i+c+b+d is even, etc h a B g b d c i C SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  29. Correction of 4-bit words (cont.) • E.g. 0011 – bits in order AB,ABC,AC,BC (alphabetic) B Even parity 1 0 0 A i.e. Memory holds 1 0 0 1 1 1 1 C 0 0011 110 data Error Occurs. Now data looks like 1011 parity bits g,h,i Two parity bits find error 1 1 1 1 1 0 1 1 0 1 1 1 0 0 SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  30. Advanced DRAM Organization • Basic DRAM same since first RAM chips • Enhanced DRAM • Contains small SRAM as well • SRAM holds last line read (c.f. Cache!) • Cache DRAM • Larger SRAM component • Use as cache or serial buffer SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  31. Synchronous DRAM (SDRAM) • Access is synchronized with an external clock • Address is presented to RAM • RAM finds data (CPU waits in conventional DRAM) • Since SDRAM moves data in time with system clock, CPU knows when data will be ready • CPU does not have to wait, it can do something else • Burst mode allows SDRAM to set up stream of data and fire it out in block • DDR-SDRAM sends data twice per clock cycle (leading & trailing edge) SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  32. IBM 64Mb SDRAM Operation mode register value determines burst length and latency SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  33. IBM 64Mb SDRAM Block Diagram SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  34. RAMBUS DRAM (RDRAM) • Adopted by Intel for Pentium & Itanium • Main competitor to SDRAM • Vertical package – all pins on one side • Data exchange over 28 wires < 12 cm long • Bus addresses up to 320 RDRAM chips at 1.6Gbps • Asynchronous block protocol • 480ns initial access time • Then 1.6 Gbps data rate latency burst SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  35. RAMBUS Diagram To processor “Smart” SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

  36. “Recent” Memory Offerings (circa 2002) Note: Price for RDRAM 512MB 1024MB Why? (What is ECC?) SYSC 2001* - Fall 2007. SYSC2001-Ch5.ppt

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