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Verilog HDL Design 期中上機考試

Verilog HDL Design 期中上機考試. 2009/11/9. Problems. Design a 4-to-16 decoder with non-inverted output using at most five enable-controlled 2-to-4 decoders. Write a test bench to instantiate it and verify the results. (25%)

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Verilog HDL Design 期中上機考試

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  1. Verilog HDL Design期中上機考試 2009/11/9

  2. Problems • Design a 4-to-16 decoder with non-inverted output using at most five enable-controlled 2-to-4 decoders. Write a test bench to instantiate it and verify the results. (25%) • See the following slides. Please design a n-bit ALU and its corresponding ALU control circuit. Write a test bench to instantiate a 32-bit ALU with ALU control and verify the results. (75%) • Requirements: Using ModelSim for your design.

  3. Datapath With Control

  4. 32-bit ALU • Create a paramaterized ALU • Input • 4-bit control + n-bit A + n-bit B • Output • n-bit Result + 1-bit Zero flag §4.4 A Simple Implementation Scheme

  5. ALU Control • Assume 2-bit ALUOp derived from opcode • Combinational logic derives ALU control

  6. 0 4 35 or 43 rs rs rs rt rt rt rd address address shamt funct 31:26 31:26 31:26 25:21 25:21 25:21 20:16 20:16 20:16 15:11 10:6 15:0 15:0 5:0 The Main Control Unit • Control signals derived from instruction R-type Load/Store Branch opcode always read read, except for load write for R-type and load sign-extend and add

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