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ISPSD’05 Highlights

ISPSD’05 Highlights. MultiMarket Semiconductors BL Power Management 14th June 2005. ISPSD05. International Symposium on Power Semiconductor Devices and ICs 2005 Rotates USA -> Europe -> Japan This year in Santa Barbara, California (next year Naples) 13 paper sessions

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ISPSD’05 Highlights

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  1. ISPSD’05 Highlights MultiMarket Semiconductors BL Power Management 14th June 2005

  2. ISPSD05 • International Symposium on Power Semiconductor Devices and ICs 2005 • Rotates USA -> Europe -> Japan • This year in Santa Barbara, California (next year Naples) • 13 paper sessions • 1 on Superjunction MOSFETS* • 1 on Novel Low-Voltage Devices* • 2 on SOI Power ICs • 2 on IGBTs • 3 on new materials (SiC, GaN) • 2 on LDMOS reliability • 2 on Power ICs • Poster session • Plenary session • Discussion Panels* • Short Course*

  3. ISPSD’05 Impressions • Several papers/posters on superjunction devices • Very little on LV discrete Trench this year • 3 other good sessions: • Short course on Low Voltage Power Devices for Portable Systems (Mohamed Darwish – Fairchild)* • Short Course on Superjunction Power Devices (Paul Chow – Rensselaer)* • Panel Discussion on Advanced Si, SiC and GaN Technologies • * interest in separate session on these highlights?

  4. For more detail………….. • CD rom and printed proceedings available • For both Main Conference and Short Course • pdfs of all papers, posters and short-course presentations available via: • I:\devel\ispsd\2005\toc.pdf • Some brief highlights…………………..

  5. P27 – Toshiba ‘Over 1000V Semi-Superjunction MOSFET with Ultra-Low On-Resistance’ • Top half = COOLMOS process/ structure • 6 epi steps • 8um pitch • Bottom half = conventional • Trade-off of cost and performance

  6. P27 – Toshiba ‘Over 1000V Semi-Superjunction MOSFET with Ultra-Low On-Resistance’ • Top half = COOLMOS process/ structure • Bottom half = conventional • Still beats 1D limit • Consider the concept for RSO?

  7. P27 – Toshiba ‘Over 1000V Semi-Superjunction MOSFET with Ultra-Low On-Resistance’ • Top half = COOLMOS process/ structure • Bottom half = conventional • Trade-off of cost and performance • Softer recovery than CoolMOS

  8. P 31 – Fuji ‘Above 500V class Superjunction by deep trench etching and epi growth’ • Lower cost than CoolMOS • Lower Rspec via reduced pitch? • In practice slightly worse • Key issue is doping control

  9. P 31 – Fuji ‘Above 500V class Superjunction by deep trench etching and epi growth • Lower cost than CoolMOS • Performance slightly worse • Key issue is doping control

  10. P 35 – Philips ‘Scalable trench etch based process for HV vertical RESURF MOSFETS • Extension of PRLe VPD deep trench to 600V (470V in paper) • Process/design re-arranged to reduced stress on TEOS and avoid exposing voids • Queries on ruggedness and reliability

  11. P 35 – Philips ‘Scalable trench etch based process for HV vertical RESURF MOSFETS

  12. P 35 – Philips ‘Scalable trench etch based process for HV vertical RESURF MOSFETS • Extension of PRLe VPD deep trench to 600V (470V in paper) • Process/design re-arranged to reduced stress on TEOS and avoid exposing voids • Beats CoolMOS on cost and performance • X6 below 1D

  13. P 35 – Philips ‘Scalable trench etch based process for HV vertical RESURF MOSFETS • Superjunctions have improved Rds(on) temp coefficients via higher epi doping

  14. P39 – NEC ‘High Performance UMOSFETs with Split P-Columns fabricated by Multi-Ion-Implant’ • CoolMOS-like structure via several (N=1,2,4) P+ implants with different energies • Lower voltage (40-75V), limited by implant energy and masking considerations • 1.5MeV max for 2.5um depth • Query on dynamic behaviour of floating regions

  15. P39 – NEC ‘High Performance UMOSFETs with Split P-Columns fabricated by Multi-Ion-Implant’ • CoolMOS-like structure via varying energy P implants • Lower voltage, limited by implant energy and masking considerations • Performance similar to RSO

  16. P43 – Toyota ‘Floating Island and Thick Bottom Oxide MOSFET (FITMOS)’ • Deep trenches • Boron implant in bottom • Partial oxide refill • Conventional top structure

  17. P43 – Toyota ‘Floating Island and Thick Bottom Oxide MOSFET (FITMOS)’ • Deep trenches • Boron implant in bottom • Partial oxide refill • Conventional top structure

  18. P43 – Toyota ‘Floating Island and Thick Bottom Oxide MOSFET (FITMOS)’ • Mix of lateral scaling and reduced drift resistance • 2.5um pitch • 2.5um trench depth • Simulation predicts • 27mohm mm2 (70V) • Low R.Qgd • X2 softer recovery • Query on dynamic behaviour

  19. P43 – Toyota ‘Floating Island and Thick Bottom Oxide MOSFET (FITMOS)’

  20. P43 – Toyota ‘Floating Island and Thick Bottom Oxide MOSFET (FITMOS)’ • Slightly better than RSO?

  21. P47 – National Semi ‘Monolithic Integration of Trench Vertical DMOS into a BCD Process’ • Needs buried N+ layer and periodic sinkers to bring drain to top surface • Only 1 extra mask to BCD process • 4um pitch

  22. P47 – National Semi ‘Monolithic Integration of Trench Vertical DMOS into a BCD Process’ • Needs buried N+ layer and periodic sinkers to bring drain to top surface

  23. P47 – National Semi ‘Monolithic Integration of Trench Vertical DMOS into a BCD Process’

  24. P147 – TI ‘Wafer Chip Scale Packages with Small Foot-Print for Portable Applications’

  25. P147 – TI ‘Wafer Chip Scale Packages with Small Foot-Print for Portable Applications’

  26. P147 – TI ‘Wafer Chip Scale Packages with Small Foot-Print for Portable Applications’

  27. P147 – TI ‘Wafer Chip Scale Packages with Small Foot-Print for Portable Applications’

  28. P175 – Renesas ‘Low loss and small SiP for DC-DC Converters’

  29. P175 – Renesas ‘Low loss and small SiP for DC-DC Converters’

  30. P175 – Renesas ‘Low loss and small SiP for DC-DC Converters’

  31. P259 – IR ‘Localised Lifetime and Resistivity control by Helium Implant’ • One of several alternative lifetime control options

  32. P355 – Fuji ‘Integrated Bi-directional Trench lateral Power MOSFETs for battery protection ICs’

  33. P355 – Fuji ‘Integrated Bi-directional Trench lateral Power MOSFETs for battery protection ICs’

  34. P355 – Fuji ‘Integrated Bi-directional Trench lateral Power MOSFETs for battery protection ICs’

  35. P355 – Fuji ‘Integrated Bi-directional Trench lateral Power MOSFETs for battery protection ICs’

  36. For more detail………….. • CD rom and printed proceedings available • For both Main Conference and Short Course • pdfs of all papers, posters and short-course presentations available via: • I:\devel\ispsd\2005\toc.pdf • Let me know if there’s interest in another session to review the short course presentations

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