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COE 308

COE 308. MIPS Instructions. MIPS. M icroprocessor without I nterlocked P ipeline S tages. RISC microprocessor architecture developed by MIPS Computer Systems Inc.

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COE 308

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  1. COE 308 MIPS Instructions COE 308

  2. MIPS Microprocessor without Interlocked Pipeline Stages • RISC microprocessor architecture developed by MIPS Computer Systems Inc. • MIPS designs are used in SGI's computer product line, and have found broad application in embedded systems, Windows CE devices, and Cisco routers. • The Nintendo 64 console, Sony Playstation console, Sony Playstation 2 console, and Sony Playstation Portable handheld system use MIPS processors. • By the late 1990s it was estimated that one in three RISC chips produced were MIPS-based designs. COE 308

  3. Instructions in MIPS • Reduced Instruction Set • 3 Operands per operation: 2 sources and 1 destination • Most instructions are of the form: Operation dst, src1, src2 Where it means: dst  src1 Operation src2 Example: addition add dst, src1, src2 means: dst  src1 + src2 COE 308

  4. Operands • 32 General-purpose registers: R0 – R31 • R0 is “wired” to the value “0” • Writing to R0 does not change its value • Special-purpose registers LO and HI • Hold results of integer multiply and divide • Special-purpose program counter PC • 32 Floating Point Registers (FPRs) • Floating Point Unit (FPU) can be either 32-bit or 64-bit • FPRs are 32 bits on a 32-bit FPU, and 64 bits on a 64-bit FPU • Almost all instructions operate on registers • All destination operands are registers • One of the source operands is a signed/unsigned 16-bits immediate value COE 308

  5. Instruction Format • Fixed Format • 3 Format Types • Register: R-type • Immediate: I-type • PC-relative: J-type 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS Instructions Format COE 308

  6. R-Type • Used by • Arithmetic Instructions • Logic Instructions • Except when Immediate Addressing mode used op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits COE 308

  7. I-Type • Used by • Instructions using Immediate addressing mode • Instructions using Displacement addressing mode • Branch instructions op rs rt address/immediate 6 bits 5 bits 5 bits 16 bits COE 308

  8. J-Type • Used by • Jump Instructions op target address 6 bits 26 bits COE 308

  9. Instructions • Arithmetic and Logic Instructions • Comparison Instructions • Load/Store and Data Movement Instructions • Branch and Jump Instructions COE 308

  10. Arithmetic & Logic Instructions small circle in front of the instruction means that it is a pseudo-instruction COE 308

  11. Addressing Modes The second operand of all of the load and store instructions must be an address. The MIPS architecture supports the following addressing modes: COE 308

  12. Load Instructions COE 308

  13. Store Instructions COE 308

  14. Data Movements Instructions The data movement instructions move data among registers. Special instructions are provided to move data in and out of special registers such as hi and lo. COE 308

  15. Exceptions COE 308

  16. Assembly Conventions COE 308

  17. Comments, Labels, Registers and Directives • Comment: • “#”: • Label: • <label:> • Registers • $<register_number> or $<register_label> • Directives • .data: for defining the constant segment • .text: for defining the code • .ascii: for defining strings • .asciiz: for defining zero-terminated strings • .byte: for defining constants COE 308

  18. Registers Even though any of the registers can theoretically be used for any purpose, MIPS programmers have agreed upon a set of guidelines that specify how each of the registers should be used. Programmers (and compilers) know that as long as they follow these guidelines, their code will work properly with other MIPS code. COE 308

  19. SPIM Simulator Source code: text file saved as with “.asm” extension. COE 308

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