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Chapter 6 Component Test and Verification Modified from Prof. Navabi’s Lectures

Chapter 6 Component Test and Verification Modified from Prof. Navabi’s Lectures. Component Test and Verification. 6.1 Testbench 6.1.1 Combinational circuit testing 6.1.2 Sequential circuit testing 6.2 Testbench Techniques 6.2.1 Test data 6.2.2 Simulation control

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Chapter 6 Component Test and Verification Modified from Prof. Navabi’s Lectures

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  1. Chapter 6 Component Test and Verification Modified from Prof. Navabi’s Lectures

  2. Component Test and Verification 6.1 Testbench 6.1.1 Combinational circuit testing 6.1.2 Sequential circuit testing 6.2 Testbench Techniques 6.2.1 Test data 6.2.2 Simulation control 6.2.3 Limiting data sets 6.2.4 Applying synchronized data 6.2.5 Synchronized display of results 6.2.6 An interactive testbench 6.2.7 Random time intervals 6.2.8 Buffered data application

  3. Component Test and Verification 6.3 Design Verification 6.4 Assertion Verification 6.4.1 Assertion verification benefits 6.4.2 Open verification library 6.4.3 Using assertion monitors 6.4.4 Assertion templates 6.5 Text Based Testbenches 6.6 Summary

  4. Component Test and Verification • This chapter shows: • How Verilog language constructs can be used for application of data to a module under test (MUT) • How module responses can be displayed and checked • The first part: Data application and response monitoring • The second part: The use of assertion verification for giving a better observability to our design modules

  5. Testbench • Verilog simulation environments provide two kinds of display of simulation results: • Graphical • Textual • Some also provide tools for editing input test data to a design module that is being tested. • These tools are referred to as Waveform Editors. • Waveform editors have 2 problems: • Usually are good only for small designs. • Each simulation environment uses a different procedure for waveform editing. • This problem can be solved by use of Verilog Testbenches.

  6. Testbench • A Verilog Testbench is: • A Verilog module • Instantiates Module Under Test (MUT). • Applies data to MUT. • Monitors the output. • A module and its testbench forms a Simulation Module in which MUT is tested for the same data regardless of what simulation environment is used.

  7. Testbench

  8. Combinational Circuit Testing

  9. Combinational Circuit Testing module alu_4bit (a, b, f, oe, y, p, ov, a_gt_b, a_eq_b, a_lt_b); input [3:0] a, b; input [1:0] f; input oe; output [3:0] y; output p, ov, a_gt_b, a_eq_b, a_lt_b; // . . . endmodule Data Inputs Function Input Data Output Compare Outputs Parity Output Overflow Output • alu_4bit Module Declaration

  10. Variables connecting to Inputs Variables connecting to Outputs Combinational Circuit Testing module test_alu_4bit; reg [3:0] a=4'b1011, b=4'b0110; reg [1:0] f=2'b00; reg oe=1; wire [3:0] y; wire p, ov, a_gt_b, a_eq_b, a_lt_b; alu_4bit cut( a, b, f, oe, y, p, ov, a_gt_b, a_eq_b, a_lt_b ); ....................... ....................... This instantiation associates local regs and wires to the ports of the alu_4bit module • Testbench for alu_4bit

  11. Every 20 ns A new value is assigned to b Combinational Circuit Testing Application of data to the b data imput and oe output-enable ....................... initial begin #20 b=4'b1011; #20 b=4'b1110; #20 b=4'b1110; #80 oe=1'b0; #20 $finish; end always #23 f = f +1; endmodule Initial Block Waits for 80ns The $finish statement is reached at 160 ns. At this time all active procedural blocks stop and simulation terminates. Disables the ALU Output by setting oe to 0 Application of data to the f input. f is increment by 1 every 23 ns. Allows effects of the last input change to be shown in simulation results After 20ns the simulation is finished • Testbench for alu_4bit (Continued)

  12. Combinational Circuit Testing f changes every 23ns causing various ALU functions to be examined At 140 ns oe changes to 0 causing the y output become Z Throughout the simulation a remains constant • ALU Simulation Results

  13. Sequential Circuit Testing Sequential Circuit Testing

  14. Sequential Circuit Testing • Testing sequential circuits involves synchronization of Clock with other data inputs.

  15. Sequential Circuit Testing The circuit has a poly parameter that determines its signature and data compression. With each clock a new signature will be calculated with the new data and existing misr register data. module #(parameter [3:0] poly=0) misr (input clk,rst, input [3:0] d_in, output reg [3:0] d_out ); always @( posedge clk ) if( rst ) d_out =4'b0000; else d_out = d_in ^ ({4{d_out[0]}} & poly) ^ {1'b0,d_out[3:1]}; endmodule • misr Sequential Circuit

  16. Sequential Circuit Testing module test_misr; reg clk=0, rst=0; reg [3:0] d_in; wire [3:0] d_out; misr #(4'b1100) MUT ( clk, rst, d_in, d_out ); ........................... ........................... Specification of the poly parameter • A Testbench for misr

  17. The initial block generates a positive pulse on rst that begins at 13 ns and ends at 63 ns. Generate data on d_in and clk Sequential Circuit Testing The timing is so chosen to cover at least one positive clock edge In order to reduce chance of several inputs changing at the same time, we usually use prime numbers for timing of sequential circuit inputs. • .......................... • initial begin • #13 rst=1'b1; • #19 d_in=4'b1000; • #31 rst=0'b0; • #330 $finish; • end • always #37 d_in = d_in + 3; • always #11 clk = ~clk; • endmodule d_in data input is initialized to 4’b1000 d_in input is assigned a new value every 37 ns. Toggles every 11ns • A Testbench for misr (Continued)

  18. Sequential Circuit Testing • Testing misr

  19. Testbench Techniques

  20. Testbench Techniques module moore_detector (input x, rst, clk, output z ); parameter [1:0] a=0, b=1, c=2, d=3; reg [1:0] current; always @( posedge clk ) if ( rst ) current <= a; .......................... .......................... endmodule Synchronous Reset Input • 101 Moore Detector for Test

  21. Testbench Techniques .......................... if ( rst ) current = a; else case ( current ) a : current <= x ? b : a ; b : current <= x ? b : c ; c : current <= x ? d : a ; d : current <= x ? b : c ; default : current <= x; endcase assign z = (current==d) ? 1'b1 : 1'b0; endmodule z output becomes 1 in state d when a sequence of 101 is detected on x • 101 Moore Detector for Test (Continued)

  22. Test Data

  23. Test Data module test_moore_detector; reg x, reset, clock; wire z; moore_detector MUT ( x, reset, clock, z ); ............................ ............................ endmodule • Basic Data Generation

  24. Four Procedural Blocks Test Data Initial Block For initializing the reg variables ............................ ............................ initial begin clock=1'b0; x=1'b0; reset=1'b1; end initial #24 reset=1'b0; always #5 clock=~clock; always #7 x=~x; endmodule The waveform generated on x may or may not be able to test our machine for a correct 101 sequence. Generates a signal with a period of 10ns on clock Generates a signal on x with a period of 14ns Variables used in the left-hand-sides in the procedural blocks are declared as reg Periods of clock and x can be changed to make this happen • Basic Data Generation (Continued)

  25. Simulation Control

  26. Simulation Control Another testbench for moore_detector which adds another initial block that stops the simulation at 189 ns. Simulation Control Tasks are $stop and $finish module test_moore_detector; reg x=0, reset=1, clock=0; wire z; moore_detector MUT ( x, reset, clock, z ); initial #24 reset=1'b0; always #5 clock=~clock; always #7 x=~x; initial #189 $stop; endmodule The first time the flow of a procedural block reaches $stop at 189 ns, simulation stops. A stopped simulation can be resumed. • Testbench with $stop Simulation Control

  27. Simulation Control Another testbench for moore_detector with $finish Control Task module test_moore_detector; reg x=0, reset=1, clock=0; wire z; moore_detector MUT ( x, reset, clock, z ); ............................ ............................ endmodule • Testbench with $finish Simulation Control

  28. Simulation Control This testbench combines the initial blocks of deactivating reset and simulation control into one initial block. ............................ ............................ initial begin #24 reset=1'b0; #165 $finish; end always #5 clock=~clock; always #7 x=~x; endmodule Simulation terminates at 165 ns. A finished simulation cannot be resumed. • Testbench with $finish Simulation Control (Continued)

  29. Limiting Data Sets

  30. Limiting Data Sets Instead of setting simulation time limit, a testbench can put a limit on the number of data put on inputs of a MUT. This will also be able to stop simulation from running indefinitely. module test_moore_detector; reg x=0, reset=1, clock=0; wire z; moore_detector MUT ( x, reset, clock, z ); initial #24 reset=1'b0; initialrepeat(13) #5 clock=~clock; initial repeat(10) #7 x=$random; endmodule Cause clock to toggle 13 times every 5 ns In large circuits, random data is more useful for data inputs than for control signals. Cause x to receive random data 10 times every 7 ns Generates random data on the x input of the circuit. • Testbench Using repeat to Limit Data Sets

  31. Applying Synchronized Data

  32. Applying Synchronized Data • Where several sets of data are to be applied: • Synchronization of data with the system clock becomes difficult. • Changing the clock frequency would require changing the timing of all data inputs of the module being tested.

  33. Applying Synchronized Data This testbench uses an event control statement to synchronize data applied to x with the clock. module test_moore_detector; reg x=0, reset=1, clock=0; wire z; moore_detector uut( x, reset, clock, z ); initial #24 reset=0; initialrepeat(13) #5 clock=~clock; initialforever @(posedge clock) #3 x=$random; endmodule This 3ns delay makes it possible to use this testbench for simulating post-synthesis designs as well as behavioral descriptions This loop waits for the positive edge of the clock, and 3 ns after it, a new random data is generated for x. Testbench Delays: Setup and Hold Time Guarantees that changing of data and clock do not coincide. • Synchronizing Data with Clock

  34. Synchronized Display of Results

  35. Synchronized Display of Results This testbench uses an event control statement for synchronized observation of MUT outputs or internal signals. module test_moore_detector; reg x=0, reset=1, clock=0; wire z; moore_detector MUT ( x, reset, clock, z ); initial #24 reset=0; initialrepeat(13) #5 clock=~clock; initial forever @(posedge clock) #3 x=$random; initial forever @(posedge clock) #1 $displayb(z); endmodule 1ns after the positive edge of the clock, when the circuit output is supposed to have its new stable value, the z output is displayed using the $displayb task. This testbench is also usable for the post-synthesis simulation of moore_detector • Testbench Displaying Output

  36. Synchronized Display of Results This testbench is developed for observing states of moore_detector module test_moore_detector; reg x=0, reset=1, clock=0; wire z; moore_detector MUT ( x, reset, clock, z ); ............................ ............................ endmodule • Testbench Displays Design Variables when they change

  37. Synchronized Display of Results Display occurs when an event occurs on one of the variables of the task’s arguments. ............................ ............................ initial #24 reset=0; initialrepeat(19) #5 clock=~clock; initial forever @(posedge clock) #3 x=$random; initial $monitor("New state is %b and occurs at %t", MUT.current, $time); always @(z) $display("Output changes at %t to %b", $time, z); endmodule Uses $monitor to display current register Starts $monitor task in the background Hierarchial Naming In binary format Event Based With the time unit Sensitive to z current state and z output are displayed when they receive new values. Flow Based Uses $display to display the output • Testbench Displays Design Variables when they change (Continued)

  38. Synchronized Display of Results New state is x and occurs at 0 Output changes at 50 to 0 New state is 0 and occurs at 50 New state is 1 and occurs at 250 New state is 2 and occurs at 850 Output changes at 950 to 1 New state is 3 and occurs at 950 • Test Results of Testbench of Fig. 6.14

  39. An Interactive Testbench

  40. An Interactive Testbench module moore_detector (input x, start, rst, clk, output z ); parameter a=0, b=1, c=2, d=3, e=4; reg [2:0] current; always @( posedge clk ) ............................ ............................ ............................ endmodule A 1101 Moore detector With 5 states • Moore Sequence Detector Detecting 1101

  41. An Interactive Testbench if ( rst ) current <= a; else if ( ~start ) current <= a; else case ( current ) a : current <= x ? b : a ; b : current <= x ? c : a ; c : current <= x ? c : d ; d : current <= x ? e : a ; e : current <= x ? c : a ; default: current <= a; endcase assign z = (current==e); endmodule If start becomes 0 the machine resets to initial state a Output becomes 1 in state e • Moore Sequence Detector Detecting 1101 (Continued)

  42. An Interactive Testbench module test_moore_detector; reg x=0, start, reset=1, clock=0; wire z; moore_detector MUT ( x, start, reset, clock, z ); ............................ ............................ ............................ endmodule • An Interactive Testbench

  43. Waits for z to become 1, After it restarts the machine Repeats the process of starting the machine and waiting for z to become 1 3 more times An Interactive Testbench To get the machine started initial begin #24 reset=1'b0; start=1'b1; wait(z==1'b1); #11 start=1'b0; #13 start=1'b1; repeat(3) begin #11 start=1'b0; #13 start=1'b1; wait(z==1'b1); end #50 $stop; end After 50 ns simulation is stopped • An Interactive Testbench (Continued)

  44. always blocks to generate clock and x input An Interactive Testbench ............................ ............................ ............................ always #5 clock=~clock; always #7 x=$random; endmodule • An Interactive Testbench (Continued)

  45. An Interactive Testbench • Waveform Resulted by the Interactive Testbench

  46. An Interactive Testbench module test_moore_detector; reg x=0, start, reset=1, clock=0; wire z; moore_detector MUT ( x, start, reset, clock, z ); initial begin #24 reset=1'b0; start=1'b1; end ............................ endmodule • Interactive Testbench Using Display Tasks

  47. An Interactive Testbench When current becomes e z is displayed ............................ always begin : Output_Display wait(MUT.current == MUT.e); $display ("$display task shows: The output is %b", z); $strobe ("$strobe task shows: The output is %b", z); #2 $stop; end always #5 clock=~clock; always #7 x=$random; endmodule Hierarchical Naming Displays as soon as program flow reaches it Displays the old value of z To observe output within a state A simulation clock cycle after e is detected, z becomes 1 and is displayed Waits for all simulation event to complete before displaying • Interactive Testbench Using Display Tasks (Continued)

  48. Random Time Intervals

  49. Random Time Intervals This testbench uses random wait times for assigning values to x module test_moore_detector; reg x, start, reset, clock; wire z; reg [3:0] t; moore_detector MUT ( x, start, reset, clock, z ); ............................ ............................ endmodule • Testbench using Random Time Intervals

  50. Waits for 13 complete clock pulses before it de-asserts the start and finishes the simulation Waits until the propagation of all signals be completed Random Time Intervals Nonblocking assignments cause intra-assignment delay values to be regarded as absolute timing values initial begin:running clock <= 1'b0; x <= 1'b0; reset <= 1'b1; reset <= #7 1'b0; start <= 1'b0; start <= #17 1'b1; repeat (13) begin @( posedge clock ); @( negedge clock ); end start=1'b0; #5; $finish; end • Testbench using Random Time Intervals (Continued)

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