FINITE STATE MACHINES (FSMs)

1. FINITE STATE MACHINES (FSMs) Dr. Konstantinos Tatas

2. Finite State Machine • A generic model for sequential circuits used in sequential circuit design ACOE161 - Digital Logic for Computers - Frederick University

3. Finite state machine block diagram • State memory: Set of n flip-flops that hold the state of the machine (up to 2^n distinct states) • Next state logic: Combinational circuit that determines the next state as a function of the current state and the input • Output logic: Combinational circuit that determines the output as a function of the current state and the input ACOE161 - Digital Logic for Computers - Frederick University

4. Finite State Machine types • Mealy machine: The output depends on the current state and input • Moore machine: The output depends only on the current state • State = output state machine: A Moore type FSM where the current state is the output ACOE161 - Digital Logic for Computers - Frederick University

5. State diagram A state diagram represents the states as circles and the transitions between them as arrows annotated with inputs and outputs ACOE161 - Digital Logic for Computers - Frederick University

6. Analysis of FSMs with D flip-flops • Determine the next state and output functions • Use the functions to create a state/output table that specifies every possible next state and output for any combination of current state and input ACOE161 - Digital Logic for Computers - Frederick University

7. EXAMPLE ACOE161 - Digital Logic for Computers - Frederick University

8. A B x A+ B+ y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 Next state equations and state table for example • A+=Ax+Bx • B+=A΄x • Y=(A+B)x΄ ACOE161 - Digital Logic for Computers - Frederick University

9. A B x A+ B+ y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 • A+=Ax+Bx • B+=A΄x • Y=(A+B)x΄ ACOE161 - Digital Logic for Computers - Frederick University

10. Sequential circuit design methodology • From the description of the functionality or the state/timing diagram find the state table • Encode the states if the state table contains letters • Find the necessary number of flip-flops • Select flip/flop type • From the state table, find the excitation tables and output tables • Using Karnaugh maps find the flip-flop input logic expressions • Draw the circuit logic diagram ACOE161 - Digital Logic for Computers - Frederick University

11. Example: Design the sequential circuit of the following state diagram ACOE161 - Digital Logic for Computers - Frederick University

12. A B x A+ B+ DA DB JA KA JB KB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 State/excitation table ACOE161 - Digital Logic for Computers - Frederick University

13. Karnaugh maps for combinational circuit ACOE161 - Digital Logic for Computers - Frederick University

14. Circuit logic diagram ACOE161 - Digital Logic for Computers - Frederick University

15. Example: counter ACOE161 - Digital Logic for Computers - Frederick University

16. Self-correcting state machines • The previous example did not include two possible states “011” and “111”. If the counter unexpectedly falls into one of those states there are two possibilities: • The counter will recover by entering a valid state after a finite number of cycles (self-correcting) • The counter will stay in a non-valid state until the f/fs are reset (not self-correcting) • Finite state machines should be designed to be self correcting by assigning non-valid states to a valid next state (no don’t cares in the excitation table) ACOE161 - Digital Logic for Computers - Frederick University

17. Example • Design a self-correcting one-digit BCD counter ACOE161 - Digital Logic for Computers - Frederick University

18. State minimization/assignment • Often the state of the circuit is not also the output and therefore the states are named abstractly • State minimization and state assignment are then required • State minimization is the simplification of the state diagram so that a circuit with less states produces the same output sequence • State assignment is the process of assigning a binary number to each state ACOE161 - Digital Logic for Computers - Frederick University

19. Example • State values are not important just the input/output sequence • States are symbolized with letters ACOE161 - Digital Logic for Computers - Frederick University

20. State table ACOE161 - Digital Logic for Computers - Frederick University

21. State equivalence • Two states are equivalent if for any element of the input set both produce the same output and send the circuit to the same state or an equivalent one. • One of the two equivalent states can be eliminated from the state diagram ACOE161 - Digital Logic for Computers - Frederick University

22. State minimization d d e ACOE161 - Digital Logic for Computers - Frederick University

23. State assignment • Since we don’t care about the actual flip-flop values for each state we can assign each state to any binary number we like as long as each state is assigned a unique binary number • If we use 3 bits to encode the states, we have possible encodings ACOE161 - Digital Logic for Computers - Frederick University

24. One-hot encoding • One flip-flop per state encoding • Leads to greater number of flip-flops than binary encoding but possibly to simpler logic ACOE161 - Digital Logic for Computers - Frederick University

25. Algorithmic State Machines

26. Introduction Digital system is specified by the following three components: • The set of registers in the system • The operations that are performed on the data stored in the registers. • The control that supervises the sequences of operations in the system. ACOE161 - Digital Logic for Computers - Frederick University

27. Control and Datapath Interaction ACOE161 - Digital Logic for Computers - Frederick University

28. Datapath • Binary information in digital systems classified as either data or control. • Data – bits of information manipulated by performing arithmetic and logic operations. • Hardware components realizing above operations are adders, decoders, multiplexers, counters e.t.c ACOE161 - Digital Logic for Computers - Frederick University

29. Control Path • Command signals used to supervise execution of algorithms by datapath. • Bi-directional communication with datapath through status conditions used to determine the sequence of control signals. • Control logic inherently sequential. • Control logic is usually implemented using FSMs ACOE161 - Digital Logic for Computers - Frederick University

30. Algorithm Implementation • Often we have to implement an algorithm in hardware instead of software • Algorithm is a well defined procedure consisting of a finite number of steps to the solution of a problem. • It is often hard to translate the algorithm into an FSM. • ASMs can serve as stand-alone sequential network model. ACOE161 - Digital Logic for Computers - Frederick University

31. Algorithmic State Machine • Used to graphically describe the operations of an FSM more concisely • Resembles conventional flowcharts – differs in • interpretation. • Conventional flowchart – sequential way of • representing procedural steps and decision paths • for algorithm • -No time relations incorporated • ASM chart – representation of sequence of • events together with timing relations between • states of sequential controller and events • occurring while moving between steps ACOE161 - Digital Logic for Computers - Frederick University

32. ASM Chart • Three basic elements: state box, decision • box and conditional box • -State and decision boxes used in conventional • flowcharts • -Conditional box characteristic to ASM • State box • -Used to indicate states in control sequence • Register operations and output signals used to • control generation of next state written ACOE161 - Digital Logic for Computers - Frederick University

33. State box • Represents one state in the ASM. • May have an optional state output list. • Single entry. • Single exit to state or decision boxes. ACOE161 - Digital Logic for Computers - Frederick University

34. State Box • State name T3 • Binary code of T3 – 011 • Register operation R <- 0 • START – name of • outputs signal generated • in this stage ACOE161 - Digital Logic for Computers - Frederick University

35. Decision box Provides for next alternatives and conditional outputs. Conditional output based on logic value of Boolean expression involving external input variables and status information. Single entry. Dual exit, denoting if Boolean expression is true or false. Exits to decision, state or conditional boxes. ACOE161 - Digital Logic for Computers - Frederick University

36. Decision Box • Input condition subject to • test inside diamond shape • box • Two or more outputs • represent exit paths • dependant on value of • condition in decision box • Two paths for binary basedconditions ACOE161 - Digital Logic for Computers - Frederick University

37. Conditional output box • Provides a listing of output variables that are to have a value logic-1, i.e., those output variables being asserted. • Single entry from decision box. • Single exit to decision or state box. ACOE161 - Digital Logic for Computers - Frederick University

38. Conditional Box • In state T1 • Output signal START • generated • Status of input E • checked • If E = 1, R <- 0, • otherwise remains • unchanged • Conditional • operation executed • depending on result • of coming from • decision box ACOE161 - Digital Logic for Computers - Frederick University

39. ASM Block • Consists of the interconnection of a single state box along with one or more decision and/or conditional boxes. • It has one entry path which leads directly to its state box, and one or more exit paths. • Each exit path must lead directly to a state, including the state box in itself. • A path through an ASM block from its state box to an exit path is called a link path. ACOE161 - Digital Logic for Computers - Frederick University

40. Timing Considerations • All sequential elements in datapath and control • path controlled by master-clock generator. • Does not necessarily imply single clock in design. • Multiple clocks can be obtained through division of clock • signals from master-clock generator. • Not only internal signals, but also inputs • synchronized with clock. • Normally, inputs supplied by other devices working • with the same master clock. • Some inputs can arrive asynchronously • Difficult to handle by synchronous designs, require • asynchronous glue-logic. ACOE161 - Digital Logic for Computers - Frederick University

41. ASM Block • In conventional flowchart, evaluation ofeach chart element takes one clock cycle • Step 1: Reg A incremented • Step 2: Condition E evaluated • Step 3: Based on evaluation results, state • T2, T3 or T4 entered • In ASM the entire block considered • as one unit • All operations within block occurring • during single edge transition • The next state evaluated during the same clock • System enters next state T2, T3 or T4 duringtransition of next clock ACOE161 - Digital Logic for Computers - Frederick University

42. ASM Block • An ASM block describes the operation of the system during the state time in which it is in the state associated with the block. • The outputs listed in the state box are asserted. • The conditions indicated in the decision boxes are evaluated simultaneously to determine which link path is to be followed. • If a conditional box is found in the selected path then the outputs found in its output list are asserted. • Boolean expression may be written for each link path. The selected link paths are those that evaluate to logic-1. ACOE161 - Digital Logic for Computers - Frederick University

43. Example 2 • Extract the FSM diagram from the ASM diagram ACOE161 - Digital Logic for Computers - Frederick University

44. Example • Design a circuit that implements the following pseudocode: a=0; for (i=0;i<5;i++) if b=0 then //boolean a = a+i; out = a; else out = a-i; ACOE161 - Digital Logic for Computers - Frederick University

45. ASM chart ACOE161 - Digital Logic for Computers - Frederick University

46. Control/datapath partitioning a=0; for (i=0;i<5;i++) if b=0 then a = a+i; out = a; else out = a-i; External control inputs: b Input data: a, i Status conditions: i< 5 Commands: i++, a = a+i, out=a, out=a-i ACOE161 - Digital Logic for Computers - Frederick University

47. Datapath design a=0; // register for a for (i=0;i<5;i++) // adder for i++ if b=0 then a = a+i; //adder for a+i out = a; else out = a-i; //adder for a-i //mux for out ACOE161 - Digital Logic for Computers - Frederick University

48. ASM chart ACOE161 - Digital Logic for Computers - Frederick University

49. Datapath design ACOE161 - Digital Logic for Computers - Frederick University

50. Control logic design • State Diagram • State encoding: • Load:00 • If: 01 • Else: 10 • End: 11 ACOE161 - Digital Logic for Computers - Frederick University